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At least 271 records · Page 15

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NASA NTRS1979

The Look-point Aircraft Coordinate Estimator (LACE) and potential applications

A look-point aircraft coordinate estimator (LACE) consisting of a windshield runway symbol projector, pilot input controls, microprocessor, and eye-alignment device is described. The estimator is used by a pilot to determine his aircraft's position relative to a runway or other visible terrain or target. The pilot initially superimposes and then corrects the superposition of the runway symbol over the runway during approach during periods when the runway is visible. Using the pilot's inputs the microprocessor calculates the position of the aircraft in terms of runway coordinates, then generates an approach trajectory and issues instructions to an autopilot. The microprocessor contains a model of the aircraft's dynamics and calculates a theoretical aircraft trajectory. The theoretical position of the aircraft is then used to drive the runway symbol, with the pilot's input being additive. The system thus acts as an aid in making low visibility approaches and landings when only an occasional glimpse of the runway is possible and no ground referenced landing systems are available. The system can also be used as an independent landing monitor for ground referenced landing systems.

Anderson, W. W.↗

NASA NTRS1979

A rocket-borne pulse-height analyzer for energetic particle measurements

The pulse-height analyzer basically resembles a time-sharing multiplexing data-acquisition system which acquires analog data (from energetic particle spectrometers) and converts them into digital code. The PHA simultaneously acquires pulse-height information from the analog signals of the four input channels and sequentially multiplexes the digitized data to a microprocessor. The PHA together with the microprocessor form an on-board real-time data-manipulation system. The system processes data obtained during the rocket flight and reduces the amount of data to be sent back to the ground station. Consequently the data-reduction process for the rocket experiments is speeded up. By using a time-sharing technique, the throughput rate of the microprocessor is increased. Moreover, data from several particle spectrometers are manipulated to share one information channel; consequently, the TM capacity is increased.

Leung, W.↗

NASA NTRS1979

Low-level processing for real-time image analysis

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

Eskenazi, R.↗

NASA NTRS1982

Programable Interface Handles Many Peripherals

Microprocessor-based interface simplifies interconnection of peripheral device with common memory of network of minicomputers. Interface consists of microprocessor, bidirectional port that connects to common memory, bidirectional port that connects to user-selected peripheral, and asynchronous serial communications port. Programable interface is based around 6800 microprocessor. It is assembled from 90 integrated circuits.

Jasinski, M.↗

NASA NTRS1981

The Lick Observatory charge-coupled device /CCD/ and controller

A description is given of a flexible microprocessor-based controller for charge-coupled device two-dimensional detectors. It is noted that the controller can operate under manual control or as a slave to a remote computer linked by coaxial cable. The system is discussed, together with data taken at the telescope and in the laboratory. The flexibility of the controller derives from its modular form and from the use of a programmable 8-bit microprocessor to control and sequence the electronic logic. The electronic circuits for such functions as signal processing, clock sequencing, voltage level adjustment, and temperature control are on small individual plug-in cards, making future improvements and changes simple. The software of the microprocessor is stored in erasable, programmable, read-only memory. Among the limitations of the controller is a scan speed of roughly 35 microsec per pixel.

Robinson, L. B.↗

NASA NTRS1983

Enhanced character sizes for the VDM-1 video display board

Use of a microprocessor for providing navigation information from the inherent hyperbolic geometries of Loran-C was discussed. The advantages Loran-C offers over VOR/DME as a primary navigation aid are identified. These advantages include long range coverage by several stations, coverage at low altitudes, and the capability to have nonprecision approaches at airports not already served by landing aids. Modern digital electronic technology is used to produce a device to convert Loran-C data to useful pilot information using simple software algorithms and low cost microprocessor devices. The cost and lack of availability of suitable processors to execute these algorithms have prevented a Loran-C navigator from being developed. Results indicate that the microprocessor based Loran-C navigator has an accuracy of 1.0 nm or less over an area typically covered by a triad of Loran-C stations and can execute a position update in less than 0.2 seconds.

Novacki, S. M., III↗

NASA NTRS1984

Smart motor technology

Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.

Packard, D.↗

NASA NTRS1984

Control methodologies for large space structures

The objectives of this research were to develop techniques of controlling a dc-motor driven flywheel which would apply torque to the structure to which it was mounted. The motor control system was to be implemented using a microprocessor based controller. The purpose of the torque applied by this system was to dampen oscillations of the structure to which it was mounted. Before the work was terminated due to the unavailability of equipment, a system was developed and partially tested which would provide tight control of the flywheel velocity when it received a velocity command in the form of a voltage. The procedure followed in this development was to first model the motor and flywheel system on an analog computer. Prior to the time the microprocessor development system was available, an analog control loop was replaced by the microprocessor and the system was partially tested.

Mcree, G. J.↗

NASA NTRS1984

A summary of JPL single event upset test data from May 1982, through January 1984

A summary of single event upset data for 42 device types (including RAMs, 4-bit slices, microprocessors, 4-bit counters, and flip-flops) studied at 11 different accelerator tests (performed chiefly with the Berkeley 88-inch cyclotron and the Cal Tech Van de Graaff) is presented. All bipolar and NMOS RAMs were found to be SEU sensitive, some with very low LET thresholds. Some CMOS or CMOS/SOS RAMs were hard; and the CMOS microprocessors were hard, but the bipolar and NMOS microprocessors were soft. Several devices were found to exhibit a cross section that depends strongly on LET, even when the LET is well above the LET threshold. A ranking of hardness is presented for the logic devices tested.

Nichols, D. K.↗

NASA NTRS1989

Rapidly quantifying the relative distention of a human bladder

A device and method of rapidly quantifying the relative distention of the bladder in a human subject are disclosed. The ultrasonic transducer which is positioned on the subject in proximity to the bladder is excited by a pulser under the command of a microprocessor to launch an acoustic wave into the patient. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer, when it is received, amplified and processed by the receiver. The resulting signal is digitized by an analog-to-digital converter under the command of the microprocessor and is stored in the data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy; and based on programmed scientific measurements and individual, anatomical, and behavioral characterists of the specific subject as contained in the program memory, sends out a signal to turn on any or all of the audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

Companion, John A.↗

NASA NTRS1990

Verifying an interactive consistency circuit: A case study in the reuse of a verification technology

The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation of a scheme for attaining interactive consistency (byzantine agreement) among four microprocessors is presented in view graph form. The microprocessors used in the design are an updated version of a formally verified 32-bit, instruction-pipelined, RISC processor, MiniCayuga. The 4-processor system, which is designed under the assumption that the clocks of all the processors are synchronized, provides software control over the interactive consistency operation. Interactive consistency computation is supported as an explicit instruction on each of the microprocessors. An identical user program executing on each of the processors decides when and on what data interactive consistency must be performed. This exercise also served as a case study to investigate the effectiveness of reusing the technology which was developed during the MiniCayuga effort for verifying synchronous hardware designs. MiniCayuga was verified using the verification system Clio which was also developed at ORA. To assist in reusing this technology, a computer-aided specification and verification tool was developed. This tool specializes Clio to synchronous hardware designs and significantly reduces the tedium involved in verifying such designs. The tool is presented and how it was used to specify and verify the interactive consistency circuit is described.

Bickford, Mark↗

NASA NTRS1991

The formal verification of generic interpreters

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.

Windley, P.↗

NASA NTRS1993

System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

Hall, William A.↗

NASA NTRS1991

Experience with custom processors in space flight applications

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.

Fraeman, M. E.↗

NASA NTRS1998

Anti-Hassle Chip

With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

Source record↗

NASA NTRS2002

Personal Cabin Pressure Monitor and Warning System

A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.

Jan A Zysko↗

NASA NTRS2004

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

Savich, Gregory R.↗

NASA NTRS1980

Automated quantitative muscle biopsy analysis system

An automated system to aid the diagnosis of neuromuscular diseases by producing fiber size histograms utilizing histochemically stained muscle biopsy tissue. Televised images of the microscopic fibers are processed electronically by a multi-microprocessor computer, which isolates, measures, and classifies the fibers and displays the fiber size distribution. The architecture of the multi-microprocessor computer, which is iterated to any required degree of complexity, features a series of individual microprocessors P.sub.n each receiving data from a shared memory M.sub.n-1 and outputing processed data to a separate shared memory M.sub.n+1 under control of a program stored in dedicated memory M.sub.n.

Castleman, Kenneth R.↗