Influence of p-n junctions on the mobile charge density in MOS transistors
MOS transistors and bipolar microcircuits mobile charge density, observing p-n junction effects
Schlegel, E. S.↗
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Capacitance voltage measurements on N-type InAs MOS diodes
Capacitance voltage measurements on interface of pyrolytically deposited n-type silicon dioxide- InAs MOS diodes as function of admittance at room and 77 K temperatures
Dockerty, R. C.↗
The effects of insulator surface-ion migration on MOS and bipolar integrated circuits
Insulator surface ion migration effects on MOS and bipolar integrated circuits, describing inversion voltage and surface conductivity and recombination velocities
Keen, R. S.↗
Beam-lead processing of complementary MOS integrated circuits
Beam-lead technology application to complementary MOS IC processing
Murray, L. A.↗
Speed enhancement of complementary MOS devices
Speed required for Sisyphus experiment on Pioneer probe was attained at supply voltage well within component limitations by combining supply voltage higher than nominal with low reactance interconnections. Speed was found to be far in excess of typical. parameters suggested by manufacturers of MOS devices.
Devlin, M.↗
Shielded silicon gate complementary MOS integrated circuit.
An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.
Lin, H. C.↗
Integrated p-channel MOS gyrator
Several circuits can be integrated into one chip for applications which require more than one gyrator. They can also be integrated with other p-channel MOS circuits to eliminate need for external connections. Devices can operate at economical low-power levels, because they use FET amplifiers that do not degrade with decreases in supply.
Hochmair, E. S.↗
Experimental investigation of a shielded complementary Metal-Oxide Semiconductor (MOS) structure
A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.
Lin, H. C.↗
Tunneling in thin MOS structures
Recent results on tunneling in thin MOS structures are described. Thermally grown SiO2 films in the thickness range of 22-40 A have been shown to be effectively uniform on an atomic scale and exhibit an extremely abrupt oxide-silicon interface. Resonant reflections are observed at this interface for Fowler-Nordheim tunneling and are shown to agree with the exact theory for a trapezoidal barrier. Tunneling at lower fields is consistent with elastic tunneling into the silicon direct conduction band and, at still lower fields, inelastic tunneling into the indirect conduction band. Approximate dispersion relations are obtained over portions of the silicon-dioxide energy gap and conduction band.
Maserjian, J.↗
Oscillations in MOS tunneling
Oscillatory deviations from Fowler-Nordheim tunneling currents were measured in MOS capacitors with oxide thicknesses ranging from 30 to 75 A. The observed variation of oscillation phases and amplitudes with oxide thickness indicates that the Si-SiO2 interface is independent of oxide thickness only for thicknesses greater than 65 A. At lower thicknesses, the barrier height at the interface decreases gradually with oxide thickness at a rate on the order of 10 mV/A. At higher thicknesses, the barrier height is 4.08 eV. The energy dispersion relation with the SiO2 conduction band is parabolic. The mean free path within the SiO2 conduction band is on the order of 13 A.
Lewicki, G.↗
Application of the MOS C-V technique to determine impurity concentrations and surface parameters on the diffused face of silicon solar cells
An experimental and theoretical investigation of the feasibility of using the MOS C-V (capacitance-voltage) technique to determine impurity and surface state concentrations on the diffused face of Si solar cells with Ta2O5 coatings. Impurity concentration 10 A from the diffused surface is found to be 2.9 times 10 to the 20th power per cu cm. Charge density in surface and oxide states is 2.1 times 10 to the 13th power per sq cm. These data agree with theoretical predictions.-
Weinberg, I.↗
A measurement technique of time-dependent dielectric breakdown in MOS capacitors
The statistical nature of time-dependent dielectric breakdown characteristics in MOS capacitors was evidenced by testing large numbers of capacitors fabricated on single wafers. A multipoint probe and automatic electronic visual display technique are introduced that will yield statistical results which are necessary for the investigation of temperature, electric field, thermal annealing, and radiation effects in the breakdown characteristics, and an interpretation of the physical mechanisms involved. It is shown that capacitors of area greater than 0.002 sq cm may yield worst-case results, and that a multipoint probe of capacitors of smaller sizes can be used to obtain a profile of nonuniformities in the SiO2 films.
Li, S. P.↗
Time-dependent MOS breakdown
A general model for time-dependent breakdown in metal-oxide-silicon (MOS) structures is developed and related to experimental measurements on samples deliberately contaminated with Na. A statistical method is used for measuring the breakdown probability as a function of log time and applied field. It is shown that three time regions of breakdown can be explained respectively in terms of silicon surface defects, ion emission from the metal interface, and lateral ion diffusion at the silicon interface.
Li, S. P.↗
Model for thickness dependence of radiation charging in MOS structures
The model considers charge buildup in MOS structures due to hole trapping in the oxide and the creation of sheet charge at the silicon interface. The contribution of hole trapping causes the flatband voltage to increase with thickness in a manner in which square and cube dependences are limiting cases. Experimental measurements on samples covering a 200 - 1000 A range of oxide thickness are consistent with the model, using independently obtained values of hole-trapping parameters. An important finding of our experimental results is that a negative interface charge contribution due to surface states created during irradiation compensates most of the positive charge in the oxide at flatband. The tendency of the surface states to 'track' the positive charge buildup in the oxide, for all thicknesses, applies both in creation during irradiation and in annihilation during annealing. An explanation is proposed based on the common defect origin of hole traps and potential surface states.
Viswanathan, C. R.↗
The charge-flow transistor - A new MOS device
A new device, the charge-flow transistor (CFT), has been developed to achieve integrated MOS compatibility in sensor applications, such as gas, humidity, and fire detection, where one is interested in monitoring the transverse resistance of a thin film. The resistive material is incorporated into the gate structure of the CFT in such a way that there is a time delay between the application of the gate-to-source voltage and the appearance of a complete channel. This time delay depends on the resistivity of the thin film. A theory of device operation is presented, together with experimental results on the first CFT's. These results confirm the principles of operation, and demonstrate the utility of the CFT for making fully integrated sensing devices.
Senturia, S. D.↗
Automated tester for MOS devices
Automated system rapidly diagnoses MOS integrated circuits. Its programed electronics investigate transistor and cell characteristics to compile data needed for screening. Program can be changed rapidly to alter test procedures, test duration, and precision.
Cockrum, R. H.↗
The effect of oxidation-expanded defects upon MOS parameters
Implantation of Ne ions was chosen as a means of introducing a uniformly distributed quantitatively controllable and reproducible amount of microdefects at the silicon surface. Each wafer was ion-implanted on one half of its surface, the other half remaining as a control. Seven implant fluences from 1 trillion to 5 by 10 to the 14th power Ne ions/sq cm were used. The fluences, as well as the concentrations of defects expanded by the subsequent gate oxidation, were correlated with seven different MOS parameters. For implant fluences of 10 to the 14th power per sq cm and above, increasing stacking-fault densities were found. The oxide defect density associated with time-dependent breakdown increased significantly with Ne dose. The presence of oxidation-expanded defects drastically increases the surface-generation velocity and decreases the bulk lifetime. Slight increases in flatband voltage and surface-state density occurred only for the wafers having the greatest defect concentrations. Oxidation of a P-containing damaged silicon surface results in a greater pileup of P at the surface than occurs for the oxidation of a similar but undamaged surface. It appears that the expanding defects restrain the diffusion of P inward from the surface.
Prussin, S.↗
Measuring charge nonuniformity in MOS devices
Convenient method of determining inherent lateral charge non-uniformities along silicon dioxide/silicon interface of metal-oxide-semiconductor (MOS) employs rapid measurement of capacitance of interface as function of voltage at liquid nitrogen temperature. Charge distribution is extracted by fast-Fourier-transform analysis of capacitance voltage (C-V) measurement.
Maserjian, J.↗