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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Performance Trade-Offs for MBG Using Different Bandgap Pairs

Present GAInP2/GAAs cell grown on Ge (or GaAs) substrates have demonstrates high efficiency, However, the individual bandgaps (1.85 eV, 1.42 eV respectively) are not the optimum match to convert the AM0 spectrum efficiently, although by reducing the thickness of the GaInP2 cell, good efficiencies have been achieved. Within the III-V alloys, modeling shows that several dual junction cells, comprising different bandgap pairs, could give higher efficiency. This paper outlines the modeling used, the bandgap pairs selected, and projections for the AM0 efficiency assuming that the effects of lattice mismatch associated with the bandgap can be reduced. We also present preliminary data on I-V performance for the selected top and bottom cells and for some full cascade cells. We have included some characterization results to check the bandgaps and lattice strain, to check how closely the fabricated cells conform to the model,

Iles, P. A.↗
NASA NTRS2004

Hydrogen Passivation of Interstitial Zn Defects in Heteroepitaxial InP Cell Structures and Influence on Device Characteristics

Hydrogen passivation of heteroepitaxial InP solar cells is of recent interest for deactivation of dislocations and other defects caused by the cell/substrate lattice mismatch that currently limit the photovoltaic performance of these devices. In this paper we present strong evidence that, in addition to direct hydrogen-dislocation interactions, hydrogen forms complexes with the high concentration of interstitial Zn defects present within the p(+) Zn-doped emitter of MOCVD-grown heteroepitaxial InP devices, resulting in a dramatic increase of the forward bias turn-on voltage by as much as 280 mV, from ~680 mV to ~960 mV. This shift is reproducible and thermally reversible and no such effect is observed for either n(+)p structures or homoepitaxial p(+)n structures grown under identical conditions. A combination of photoluminescence (PL), electrochemical C-V dopant profiling, SIMS and I-V measurements were performed on a set of samples having undergone a matrix of hydrogenation and post-hydrogenation annealing conditions to investigate the source of this voltage enhancement and confirm the expected role of interstitial Zn and hydrogen. A precise correlation between all measurements is demonstrated which indicates that Zn interstitials within the p(+) emitter and their interaction with hydrogen are indeed responsible for this device behavior.

Ringel, S. A.↗
NASA NTRS2000

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction ot the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

Biegel, Bryan A.↗
NASA NTRS2004

Silicon Carbide Diodes Characterization at High Temperature and Comparison With Silicon Devices

Commercially available silicon carbide (SiC) Schottky diodes from different manufacturers rated at 200, 300, 600, and 1200 V, were electrically tested and characterized as a function of temperature up to 300 C. Electrical tests included both steady state and dynamic tests. Steady state tests produced forward and reverse I-V characteristic curves. Transient tests evaluated the switching performance of the diodes in either a hard-switched DC to DC buck converter or a half-bridge boost converter. For evaluation and comparison purposes, the same tests were performed with current state-of-the-art ultra fast silicon (Si) pn-junction diodes of similar ratings and also a Si Schottky diode. The comparisons made were forward voltage drop at rated current, reverse current at rated voltage, and turn-off peak reverse recovery current and reverse recovery time. In addition, efficiency measurements were taken for the buck DC to DC converter using both the SiC Schottky diodes and the Si pn-junction diodes at different temperatures and frequencies. The test results showed that at high temperature, the forward voltage drop for SiC Schottky diodes is higher than the forward drop of the ultra fast Si pn-junction diodes. As the temperature increased, the forward voltage drop of the SiC Schottky increased while for the ultra fast Si pn-junction diodes, the forward voltage drop decreased as temperature increased. For the elevated temperature steady state reverse voltage tests, the SiC Schottky diodes showed low leakage current at their rated voltage. Likewise, for the transient tests, the SiC Schottky diodes displayed low reverse recovery currents over the range of temperatures tested. Conversely, the Si pn-junction diodes showed increasing peak reverse current values and reverse recovery times with increasing temperature. Efficiency measurements in the DC to DC buck converter showed the advantage of the SiC Schottky diodes over the ultra fast Si pn-junction diodes, especially at the higher temperatures and higher frequencies.

Lebron-Velilla, Ramon C.↗
NASA NTRS2005

Electrical and Optical Property of Ferroelectric BaTiO3:Eu

We studied various electrical and optical properties of Europium (1 atomic %) incorporated BaTiO3 film on n-Si(100) substrate. The thin film structure was analyzed by X-ray diffraction. Film thickness and optical refractive index were measured with an ellipsometer. P-E hysteresis measurement shows the remnant polarization of 37 micro C/sq cm in BaTiO3:Eu film. C-V measurements on the pure BaTiO3 film show recovery of capacitance across sweeping voltage ranges with a narrow transition zone due to the polarization change. On the other hand, C-V and I-V measurements on the BaTiO3:Eu film show that Europium incorporation increases positively charged states in the BaTiO3 layer such that BaTiO3:Eu/n-Si interface behaves like a leaky p-n junction.

Park, Yeonjoon↗
NASA NTRS2004

LERCIP 2004 Summary

This summer I am continuing my project from the previous two summers. My work involves ohmic contacts to N-type silicon carbide (Sic) devices. My mentor, Dr. Robert Okojie, is developing the technology behind high performance sensors and actuators for harsh environments. Sic is useful because it is able to operate at temperatures up to 600 C and it is resistant to radiation damage. This allows sensors and electronics to be placed in new locations, such as inside a jet engine or in space application without using heavy shielding. Ultimately this results in more efficient, smarter engine technology, reduced launch weights for spacecraft, and high power and high temperature electronics. A fundamental part of Sic devices is the ohmic contact. The contact is the interface between the semiconductor (Sic) and external circuitry. The current flowing in and out the devices is through the contact. Ensuring that these contacts remain ohmic (linear I-V behavior) allows us to fabricate devices that do not waste power at the metallurgical junction. Another key part is maintaining a low contact resistance. It is desired to maintain minimum energy loss by avoiding a rectifying electrical characteristic. My project is to develop and implement a testing procedure for measuring the contact resistance while the device is operating at high temperature. It is important to measure the contacts while simulating the true operating environment as closely as possible. For this reason, measurements are taken while the device is heated at intervals up to 600 C in air. To test the long tern reliability of the devices, the high temperature measurements are repeated after heating the sample for long intervals in air. A new set of data is gathered after heating for a total of 100, 200 and then 400 hours. The current as a function of voltage and the contact resistance was measured using the four point probe technique. The four point probe method is chosen because it measures contact resistance while eliminating error due to wire resistance and calibration issues.

DeAngelis, David↗
NASA NTRS2001

Microelectromechanical Systems (MEMS) Actuator for Reconfigurable Patch Antenna Demonstrated

A microstrip patch antenna with two contact actuators along the radiating edges for frequency reconfiguration was demonstrated at K-band frequencies. The layout of the antenna is shown in the following figure. This antenna has the following advantages over conventional semiconductor varactor-diode-tuned patch antennas: 1. By eliminating the semiconductor diode and its nonlinear I-V characteristics, the antenna minimizes intermodulation signal distortion. This is particularly important in digital wireless systems, which are sensitive to intersymbol interference caused by intermodulation products. 2. Because the MEMS actuator is an electrostatic device, it does not draw any current during operation and, hence, requires a negligible amount of power for actuation. This is an important advantage for hand-held, battery-operated, portable wireless systems since the battery does not need to be charged frequently. 3. The MEMS actuator does not require any special epitaxial layers as in the case of diodes and, hence, is cost effective.

Simons, Rainee N.↗
NASA NTRS2005

High Quality GaAs Growth by MBE on Si Using GeSi Buffers and Prospects for Space Photovoltaics

III-V solar cells on Si substrates are of interest for space photovoltaics since this would combine high performance space cells with a strong, lightweight and inexpensive substrate. However, the primary obstacles blocking III-V/Si cells from achieving high performance to date have been fundamental materials incompatabilities, namely the 4% lattice mismatch between GaAs and Si, and the large mismatch in thermal expansion coefficient. In this paper, we report on the molecular beam epitaxial (MBE) growth and properties of GaAs layers and single junction GaAs cells on Si wafers which utilize compositionally graded GeSi Intermediate buffers grown by ultra-high vacuum chemical vapor deposition (UHVCVD) to mitigate the large lattice mismatch between GaAs and Si. Ga As cell structures were found to incorporate a threading dislocation density of 0.9-1.5 x 10 (exp 6) per square centimeter, identical to the underlying relaxed Ge cap of the graded buffer, via a combination of transmission electron microscopy, electron beam induced current, and etch pit density measurements. AlGaAs/GaAs double heterostructures wre grown on the GeSi/Si substrates for time-resolved photoluminescence measurements, which revealed a bulk GaAs minority carrier lifetime in excess of 10 ns, the highest lifetime ever reported for GaAs on Si. A series of growth were performed to ass3ss the impact of a GaAs buffer to a thickness of only 0.1 micrometer. Secondary ion mass spectroscopy studies revealed that there is negligible cross diffusion of Ga, As and Ge at he III-V/Ge interface, identical to our earlier findings for GaAs grown on Ge wafers using MBE. This indicates that there is no need for a buffer to "bury" regions of high autodopjing,a nd that either pn or np configuration cells are easily accomodated by these substrates. Preliminary diodes and single junction Al Ga As heteroface cells were grown and fabricated on the Ge/GeSi/Si substrates for the first time. Diodes fabricated on GaAs, Ge and Ge/GeSi/Si substrate show nearly identical I-V characteristics in both forward and reverse bias regions. External quantum efficiencies of AlGaAs/GaAs cell structures grown on Ge/GeSi/Si and Ge substrates demonstrated nearly identical photoresponse, which indicates that high lifetimes, diffusion lengths and efficient minority carrier collection is maintained after complete cell processing.

Carlin, J. A.↗
NASA NTRS2005

Advances in Single and Multijunction III-V Photovoltaics on Silicon for Space Power

A collaborative research effort at MIT, Ohio State University and NASA has resulted in the demonstration of record quality gallium arsenide (GaAs) based single junction photovoltaic devices on silicon (Si) substrates. The ability to integrate highly efficient, radiation hard III-V based devices on silicon offers the potential for dramatic reductions in cell mass (approx.2x) and increases in cell area. Both of these improvements offer the potential for dramatic reductions in the cost of on-orbit electrical power. Recently, lattice matched InGaP/GaAs and metamorphic InGaP/InGaAs dual junction solar cells were demonstrated by MBE and OMVPE, respectively. Single junction GaAs on Si devices have been integrated into a space flight experiment (MISSES), scheduled to be launched to the International Space Station in March of 2005. I-V performance data from the GaAs/Si will be collected on-orbit and telemetered to ground stations daily. Microcracks in the GaAs epitaxial material, generated because of differences in the thermal expansion coefficient between GaAs and Si, are of concern in the widely varying thermal environment encountered in low Earth orbit. Ground based thermal life cycling (-80 C to + 80 C) equivalent to 1 year in LEO has been conducted on GaAs/Si devices with no discernable degradation in device performance, suggesting that microcracks may not limit the ability to field GaAs/Si in harsh thermal environments. Recent advances in the development and testing of III-V photovoltaic devices on Si will be presented.

Wilt, David M.↗
NASA NTRS2005

Single Wall Carbon Nanotube-polymer Solar Cells

Investigation of single wall carbon nanotube (SWNT)-polymer solar cells has been conducted towards developing alternative lightweight, flexible devices for space power applications. Photovoltaic devices were constructed with regioregular poly(3-octylthiophene)-(P3OT) and purified, >95% w/w, laser-generated SWNTs. The P3OT composites were deposited on ITO-coated polyethylene terapthalate (PET) and I-V characterization was performed under simulated AM0 illumination. Fabricated devices for the 1.0% w/w SWNT-P3OT composites showed a photoresponse with an open-circuit voltage (V(sub oc)) of 0.98 V and a short-circuit current density (I(sub sc)) of 0.12 mA/sq cm. Optimization of carrier transport within these novel photovoltaic systems is proposed, specifically development of nanostructure-SWNT complexes to enhance exciton dissociation.

Bailey, Sheila G.↗
NASA NTRS2003

Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

Chen, Liang-Yu↗
NASA NTRS2005

MOVPE of GaSb/InGaAsSb Multilayers and Fabrication of Dual Band Photodetectors

Metalorganic vapor phase epitaxy (MOVPE) of GaSb/InGaAsSb multilayer thin films and fabrication of bias-selectable dual band photodetectors are reported. For the dual band photodetectors the short wavelength detector, or the upper p- GaSb/n-GaSb junction photodiode, is placed optically ahead of the long wavelength one, or the lower photodiode. The latter is based on latticed-matched In0.13Ga0.87As0.11Sb0.89 with bandgap near 0.6 eV. Specifically, high quality multilayer thin films are grown sequentially from top to bottom as p+-GaSb/p-GaSb/n-GaSb/n-InGaAsSb/p-InGaAsSb/p-GaSb on undoped p-type GaSb substrate, and as n-GaSb/p-GaSb/p-InGaAsSb/n-InGaAsSb/n-GaSb on Te-doped n-type GaSb substrate respectively. The multilayer thin films are characterized by optical microscope, atomic force microscope (AFM), electron microprobe analyses etc. The photodiode mesa steps are patterned by photolithography with wet chemical etching and the front metallization is carried out by e-beam evaporation with Pd/Ge/Au/Ti/Au to give ohmic contact on both n- and p-type Sb based layer surfaces. Dark I-V measurements show typical diode behavior for both the upper and lower photodiodes. The photoresponsivity measurements indicate that both the upper and lower photodiodes can sense the infrared illumination corresponding to their cutoff wavelengths respectively, comparable with the simulation results. More work is underway to bring the long wavelength band to the medium infrared wavelength region near 4 micrometers.

Xiao, Ye-Gao↗
NASA NTRS1993

High Temperature Superconductor Josephson Weak Links

High T_c edge-geometry SNS microbridges have been fabricated using ion-damaged YBa_2Cu_3O_(7-x) (YBCO) and a nonsuperconducting phase of YBCO (N-YBCO) as normal metals. Optimization of the ion milling process used for YBCO edge formation and cleaning has resulted in ion-damage barrier devices which exhibit I-V characteristics consistent with the Resistively-Shunted-Junction (RSJ) model, with typical current densities (J_c) of approximately 5 x 10^6 A/cm^2 at 4.2 K. Characterization of N-YBCO films suggests that N-YBCO is the orthorhombic YBCO phase with oxygen disorder suppressing T_c...

Hunt, B. D.↗
NASA NTRS1995

Method for fabricating semiconductor devices

A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term in situ herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed. An alternative embodiment of the present invention comprising an additional step, namely the termination of the gallium arsenide by a two monolayer thickness of epitaxial aluminum arsenide as a diffusion barrier, enables the recovery of Schottky barrier behavior, namely a rectified I-V characteristic. The present invention provides a significant breakthrough in the fabrication of III-V semiconductor devices wherein excellent Ohmic contact and Schottky barrier interfaces to such devices can be achieved simply and inexpensively and without requiring the high temperature processing of the prior art and also without requiring the use of exotic high temperature refractory materials as substitutes for those preferred contact metals such as gold, aluminum and the like.

Kaiser, William J.↗
NASA NTRS1979

Voltage-current-power meter for photovoltaic solar arrays

A meter is disclosed for measuring the voltage, current, and power (VIP) parameters of a photovoltaic solar array, or array module, under sunlight operating conditions utilizing a variable load connected across the array and controlled by a voltage regulator which responds to the difference between the output voltage of the array and a programmed test voltage from a source which generates a single ramp voltage for measuring and recording current as a function of voltage, repeated ramp voltages at a high rate for peak output measurements or a DC voltage for VIP measurements at selected points on the I-V characteristic curve of the array. The voltage signal from a current sensing element, such as a shunt resistor in series with the variable load, is compared with the output current of a reference solar cell to provide a normalizing signal to be added to the signal from the current-sensing element in order to provide a record of array current as a function of array voltage, i.e., for all load conditions from short circuit to open circuit. As the normalized current is thus measured, an analog multiplier multiplies the array voltage and normalized current to provide a measurement of power. Switches are provided to selectively connect the power, P, current, I, or voltage, V, to a meter, directly or through a peak detector. At the same time any one of the parameters V, I and P may be recorded as a function of any other parameter.

Ross, Ronald G.↗
NASA NTRS2008

Channel Temperature Determination for AlGaN/GaN HEMTs on SiC and Sapphire

Numerical simulation results (with emphasis on channel temperature) for a single gate AlGaN/GaN High Electron Mobility Transistor (HEMT) with either a sapphire or SiC substrate are presented. The static I-V characteristics, with concomitant channel temperatures (T(sub ch)) are calculated using the software package ATLAS, from Silvaco, Inc. An in-depth study of analytical (and previous numerical) methods for the determination of T(sub ch) in both single and multiple gate devices is also included. We develop a method for calculating T(sub ch) for the single gate device with the temperature dependence of the thermal conductivity of all material layers included. We also present a new method for determining the temperature on each gate in a multi-gate array. These models are compared with experimental results, and show good agreement. We demonstrate that one may obtain the channel temperature within an accuracy of +/-10 C in some cases. Comparisons between different approaches are given to show the limits, sensitivities, and needed approximations, for reasonable agreement with measurements.

Freeman, Jon C.↗
NASA NTRS2009

Data Analysis of the Floating Potential Measurement Unit aboard the International Space Station

We present data from the Floating Potential Measurement Unit (FPMU), that is deployed on the starboard (S1) truss of the International Space Station. The FPMU is a suite of instruments capable of redundant measurements of various plasma parameters. The instrument suite consists of: a Floating Potential Probe, a Wide-sweeping spherical Langmuir probe, a Narrow-sweeping cylindrical Langmuir Probe, and a Plasma Impedance Probe. This paper gives a brief overview of the instrumentation and the received data quality, and then presents the algorithm used to reduce I-V curves to plasma parameters. Several hours of data is presented from August 5th, 2006 and March 3rd, 2007. The FPMU derived plasma density and temperatures are compared with the International Reference Ionosphere (IRI) and USU-Global Assimilation of Ionospheric Measurement (USU-GAIM) models. Our results show that the derived in-situ density matches the USU-GAIM model better than the IRI, and the derived in-situ temperatures are comparable to the average temperatures given by the IRI.

Barjatya, Aroh↗
NASA NTRS2010

Combined Space Environmental Exposure Tests of Multi-Junction GaAs/Ge Solar Array Coupons

A set of multi-junction GaAs/Ge solar array test coupons were subjected to a sequence of 5-year increments of combined environmental exposure tests. The purpose of this test program is to understand the changes and degradation of the solar array panel components, including its ESD mitigation design features in their integrated form, after multiple years (up to 15) of simulated geosynchronous space environment. These tests consist of: UV radiation, electrostatic discharge (ESD), electron/proton particle radiation, thermal cycling, and ion thruster plume exposures. The solar radiation was produced using a Mercury-Xenon lamp with wavelengths in the UV spectrum ranging from 230 to 400 nm. The ESD test was performed in the inverted-gradient mode using a low-energy electron (2.6 - 6 keV) beam exposure. The ESD test also included a simulated panel coverglass flashover for the primary arc event. The electron/proton radiation exposure included both 1.0 MeV and 100 keV electron beams simultaneous with a 40 keV proton beam. The thermal cycling included simulated transient earth eclipse for satellites in geosynchronous orbit. With the increasing use of ion thruster engines on many satellites, the combined environmental test also included ion thruster exposure to determine whether solar array surface erosion had any impact on its performance. Before and after each increment of environmental exposures, the coupons underwent visual inspection under high power magnification and electrical tests that included characterization by LAPSS, Dark I-V, and electroluminescence. This paper discusses the test objective, test methodologies, and preliminary results after 5 years of simulated exposure.

Hoang, Bao↗