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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Progress in Developing an Accelerator on a Chip
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Design and development of the HPSoC - High Pitch digitizer System-on-Chip
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Evaluation of High Temperature Microcontrollers and Memory Chips for Geothermal Applications.
Abstract not provided.
FET Junction Temperature Monitoring Using Novel On-Chip Solution
A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).
Volumetric Fiber-to-Chip Mode Converters
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Towards High-throughput Materials Advancement: Thinking About Database Management in our Studying-Polymers-on-a-Chip (SPOC) Platform
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Measurement of Magnetic Field Using System-On-Chip Sensors
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Temperature-tuned ultrafast X-ray shutter using optics-on-a-chip
Typically modulation systems are incapable of performing synchronous modulation for high-energy radiation systems. A method and system for performing high-energy synchronous radiation modulating is described. The method includes providing an oscillatory diffractive element, with the oscillatory diffractive element capable of being oscillated over a range of angles. A radiation source provides radiation to the oscillatory diffractive element. An electrical signal is provided to electrodes that oscillate the oscillatory diffractive element to modulate the radiation. A temperature controller controls the temperature of the oscillatory diffractive element to tune the oscillatory motion of the oscillatory diffractive element.
On-chip probabilistic inference for charged-particle tracking at the sensor edge
Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.
Measuring quasiparticle dynamics for particle impact reconstruction in a superconducting qubit chip
Quasiparticle poisoning following particle impacts poses a significant challenge to the development of fault-tolerant superconducting quantum computers, as a sudden excess of quasiparticles can simultaneously degrade the coherence of multiple qubits across large device arrays. In this work, we present a statistical analysis that models the time evolution of radiation-induced qubit energy relaxation through quasiparticle density dynamics. This study provides insight into quasiparticle loss processes by distinguishing between recombination and trapping decay channels and assessing their respective impact on qubit performance. We precisely measure quasiparticle recombination in multiple transmon qubits and uncover an unexpected dependence of qubit relaxation dynamics on deposited energy. By linking correlated relaxation events across qubits to ballistic phonon propagation, we introduce a statistical localization approach to extract the energy deposited in the substrate, which is in good agreement with Monte Carlo simulation. This work establishes the quantitative framework for using an arbitrary subset of superconducting transmon qubits in a QPU as energy-resolving witness particle detectors.
On-Chip Chromatic Dispersion via Multi-Mode Bragg Gratings: A Design Study
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On-chip GaN Vacuum Electron Devices
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On the Cutting of Metals: A Mechanics Viewpoint
The mechanics of large-strain deformation in cutting of metals is discussed, primarily from viewpoint of recent developments in in situ analysis of plastic flow and microstructure characterization. It is shown that a broad range of deformation parameters can be accessed in chip formation—strains of 1–10, strain rates of 10–10 5 /s, and temperatures up to 0.7T m —and controlled. This range is far wider than achievable by any other single-stage, severe plastic deformation (SPD) process. The resulting extreme deformation conditions produce a rich variety of microstructures in the chip. Four principal types of chip formation—continuous, shear-localized, segmented, and mushroom-type—as elucidated first by Nakayama (1974, “The Formation of ‘Saw-Toothed Chip’ in Metal Cutting,” Proceedings of International Conference on Production Engineering, Tokyo, pp. 572–577) are utilized to emphasize the diverse plastic flow phenomena, especially unsteady deformation modes that prevail in cutting. These chip types are intimately connected with the underlying flow, each arising from a distinct mode and triggered by an instability phenomenon. The role of plastic flow instabilities such as shear banding, buckling, and fracture in mediating unsteady flow modes is expounded, along with consequences of the flow modes and chip types for the cutting. Sinuous flow is shown to be the reason why gummy (highly strain-hardening) metals, although relatively soft, are so difficult to cut. Synthesizing the various observations, a hypothesis is put forth that it is the stability of flow modes that determines the mechanics of cutting. Furthermore, this leads to a flow-stability phase diagram that could provide a framework for predicting chip types and process attributes.
Dual-scale folding in cutting of commercially pure aluminum alloys
We examine a, hitherto, little-studied and curious machining chip morphology, with tell-tale signs of folding at two different length scales, that is common in cutting of certain ductile and highly strain-hardening metals like soft aluminum alloys, tantalum and niobium. This chip morphology does not appear in the usual catalogues of common chip types. The mechanics of formation of the “dual-scale folded chip” is studied in model material systems of commercially pure aluminum alloys (AA 1100 and AA 8040), that prominently exhibit this chip morphology. The flow, folding and associated plastic instabilities are investigated using micro/macro structure observations of the chip in a plane-strain cutting framework, with high-speed in situ imaging and image analysis of material flow; and force measurements. The smaller-scale folding is shown to develop in the primary deformation zone while the larger-scale folding occurs as the chip traverses the rake face of the tool. The resulting chip is composed of irregularly-spaced large folds, superimposed onto which are the quasi periodic small folds. The representative wavelengths of the two folds differ on average by an order of magnitude, 0.1 mm vs. 2 mm. The observations reveal a direct coupling between the material flow and chip morphology, and how specific attributes of the dual-scale folded chip arise from the flow mechanism. Plastic buckling is found to play a key role in the folding at both length scales. The small-scale folds are characteristic of a sinuous plastic flow mode, while the large-scale folding is characterized by buckling and stick-slip along the tool rake face, triggered by adhesive pinning of the chip to the tool. Important consequences of the dualscale folding are very large cutting forces, and force oscillations of large amplitude, despite the alloys being very soft, only ~ 25 HV. Here, the dual-scale folding is why many of these alloys are classified as “gummy” to machine. Since the dual-scale folded chip is associated with large cutting forces and poor surface quality, there is much to be gained by disrupting this flow type in practical machining applications. Methods for controlling the folding to improve machining performance with the gummy alloys are briefly discussed.
RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades
The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.
Better Than Worst-Case Decoding for Quantum Error Correction
The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.
High-density integrated delay line using extreme skin-depth subwavelength grating waveguides
Optical delay lines control the flow of light in time, introducing phase and group delays for engineering interferences and ultrashort pulses. Photonic integration of such optical delay lines is essential for chip-scale lightwave signal processing and pulse control. However, typical photonic delay lines based on long spiral waveguides require extensively large chip footprints, ranging from mm 2 to cm 2 scales. Here we present a scalable, high-density integrated delay line using a skin-depth engineered subwavelength grating waveguide, i.e., an extreme skin-depth (eskid) waveguide. The eskid waveguide suppresses the crosstalk between closely spaced waveguides, significantly saving the chip footprint area. Our eskid-based photonic delay line is easily scalable by increasing the number of turns and should improve the photonic chip integration density.