The DUV Stability of Superlattice-Doped CMOS Detector Arrays
No abstract available
molecular beam epitaxy↗
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Results for “'CMOS',”
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Non-Destructive Measurements for CMOS Devices Using Charge Collection Techniques
Results of an experiment providing initial validation of the use of charge collection spectroscopy to measure the over-layer and epitaxial thickness and substrate diffusion length are given for several CMOIS SRAM test devices.
charge↗
3D integration of high-density CMOS circuits to high resistivity silicon detector layer
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3D integration, TSV, CMOS, ROIC, Detector↗
Digital pixel test structures implemented in a 65 nm CMOS process
The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65 nm process for use in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20–40 µm and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article. The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at + 20 °C and a detection efficiency of 99% for a DPTS irradiated with a dose of 10 15 1 MeV n eq cm -2 . Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS
One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach
Parameter extraction of compact transistor models is an expensive process, heavily relying on engineering knowledge and experience. To automate such a process, we propose a novel approach, Graph-based Compact Model (GCM), that integrates physical modeling and data-driven learning. GCM utilizes Graph Neural Networks (GNNs) to establish the model structure, while retaining the physicality in compact models. Here, we implement our GCM in Verilog-A to support circuit simulations. As demonstrated with an academic 7 nm FinFET PDK, the new approach automatically generates a GCM model within a minute, and achieves excellent accuracy and efficiency in SPICE.
42 ENGINEERING↗
A room-temperature polarization-sensitive CMOS terahertz camera based on quantum-dot-enhanced terahertz-to-visible photon upconversion
Detection of terahertz (THz) radiation has many potential applications, but presently available detectors are limited in many aspects of their performance, including sensitivity, speed, bandwidth and operating temperature. Most do not allow the characterization of THz polarization states. Recent observation of THz-driven luminescence in quantum dots offers a possible detection mechanism via field-driven interdot charge transfer. Here, we demonstrate a room-temperature complementary metal–oxide–semiconductor THz camera and polarimeter based on quantum-dot-enhanced THz-to-visible upconversion mechanism with optimized luminophore geometries and fabrication designs. Besides broadband and fast responses, the nanoslit-based sensor can detect THz pulses with peak fields as low as 10 kV cm–1. A related coaxial nanoaperture-type device shows a to-date-unexplored capability to simultaneously record the THz polarization state and field strength with similar sensitivity.
77 NANOSCIENCE AND NANOTECHNOLOGY↗
High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture
Abstract Recent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.
47 OTHER INSTRUMENTATION↗
High spatial resolution direct conversion amorphous selenium X-ray detectors with monolithically integrated CMOS readout
Recent progress in the field of micron-scale spatial resolution direct conversion X-ray detectors for high-energy synchrotron light sources serve applications ranging from nondestructive and noninvasive microscopy techniques which provide insight into the structure and morphology of crystals, to medical diagnostic measurement devices. Amorphous selenium ( a -Se) as a wide-bandgap thermally evaporated photoconductor exhibits ultra-low thermal generation rates for dark carriers and has been extensively used in X-ray medical imaging. Being an amorphous material, it can further be deposited over large areas at room temperatures and at substantially lower costs as compared to crystalline semiconductors. Here, to address the demands for a high-energy and high spatial resolution X-ray detector for synchrotron light source applications, we have thermally evaporated a -Se on a Mixed-Mode Pixel Array Detector (MM-PAD) Application Specific Integrated Circuit (ASIC). The ASIC format consists of 128 × 128 square pixels each 150 μm on a side. A 200 μm a -Se layer was directly deposited on the ASIC followed by a metal top electrode. The completed detector assembly was tested with 45 kV Ag and 23 kV Cu X-ray tube sources. The detector fabrication, performances, Modulation Transfer Function (MTF) measurements, and simulations are reported.
36 MATERIALS SCIENCE↗
The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit
We report a very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS
Not Available
Wen, Xianshan↗
110–140-GHz Wide-IF-Band 65-nm CMOS Receiver Design for Fusion Plasma Diagnostics
Not provided.
Engineering↗
Cryogenic Characterization of a 5-6 GHz LC VCO for CMOS-Quantum Co-Integration
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47 OTHER INSTRUMENTATION↗