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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Microshutter Arrays for NIRSpec

A primary science goal of the 6.5 m James Webb Space Telescope is to characterize the epoch of initial galaxy formation, observing the early universe as the first stars and galaxies formed. This program will be accomplished using a combination of multi-band imaging and spectroscopic measurements of large numbers of faint galaxies. Since these objects are in general sparse on the sky, a multi object spectrometer is required to enable this critical scientific investigation. We have developed a microshutter array which is to be used as a high contrast, remotely programmable field selector for the Near Infrared Spectrometer (NIRSpec) on JWST. This device allows slits to be opened at the locations of selected galaxies in the field of view, and blocks sources and background light from the rest of the field. The first flight design devices have been built and were tested. These first generation of devices were used to demonstrate performance and flight readiness. Devices of the same design will be delivered to ESA for installation into the NIRSpec instrument.

Silverberg, Robert↗
NASA NTRS2008

FPGA Control System for the Automated Test of Microshutters

The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

Lyness, Eric↗
NASA NTRS2008

FPGA Control System for the Automated Test of MicroShutters

The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light from an arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

Lyness, Eric↗
NASA NTRS2008

Column Grid Array Rework for High Reliability

Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.

high reliability↗
NASA NTRS2010

Methods and circuitry for reconfigurable SEU/SET tolerance

A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.

Shuler, Jr., Robert L.↗
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
DOE OSTI2023

Face‐on Orientation Matches Vertical Organic Electrochemical Transistors for High Transconductance and Superior Non‐Volatility

Abstract The recently developed vertical structure of organic electrochemical transistors (OECTs) can integrate volatile and non‐volatile functions into one reconfigurable device, making it highly promising. However, comparing with the conventional planar OECT (c‐OECT), the understanding of vertical OECT (v‐OECT) working principles and device engineering strategies is still lacking, impeding rational optimization. Since a major difference between c‐ and v‐OECTs is their charge transport directionality, which is highly influenced by crystallite orientations, the orientation–device structure match thus becomes an important yet outstanding topic for OECTs. Herein, using ann‐type small molecule IDIC‐MEG, investigate how much impact such match can have on OECT performance. The IDIC‐MEG c‐OECT fails to work due to the seriously hindered in‐plane electron transport by face‐on orientation. Surprisingly, simply changing the device structure from planar to vertical allows the resultant v‐OECT to exhibit the highest reported transconductance (46.3 mS) among all small‐molecule OECTs, thanks to the match between face‐on orientation and the vertical structure. Such match also leads to excellent non‐volatility, including highly predictable programmability and good operational stability. This work, for the first time, explicitly demonstrates the significance of orientation–device structure match for OECT optimization, establishing new guidelines for achieving high‐performance volatile and non‐volatile OECTs.

Chemistry↗
DOE OSTI2025

Automated Programmable Logic Controller Memory Forensics Using RGB Image Analysis and Deep Learning

The introduction of Industry 4.0 and Internet-based technologies has enhanced industrial control system operations but have inadvertently increased their vulnerabilities to cyber attacks. When an industrial control system is compromised, security analysts need to identify the root cause quickly to start the recovery process and develop mitigation strategies. Memory forensics is critical in the incident analysis process to ascertain what occurred. Approaches for analyzing the persistent memory in industrial control devices are limited and almost nonexistent for volatile memory. This chapter proposes an automated methodology for programmable logic controller memory dump analysis using computer vision and deep learning techniques. The methodology converts the sequences of bytes in a programmable logic controller memory dump to red-green-blue pixels and employs a deep learning model that learns the underlying patterns and features of pre-labeled forensic artifacts in images and segments them into distinct regions. The trained model is employed to automatically segment new memory images and identify forensic artifacts. Evaluation of the methodology on a Schneider Electric Modicon M221 programmable logic controller under code injection and code modification attacks demonstrates its ability to detect attack artifacts in memory dumps.

Asmar Awad, Rima [ORNL] (ORCID:0000000233407742)↗
NASA NTRS2009

Board Saver for Use with Developmental FPGAs

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Berkun, Andrew↗
DOE OSTI2023

Millimeter-Thick Liquid Crystalline Elastomer Actuators Prepared by-Surface-Enforced Alignment

Here, liquid crystalline elastomers (LCE) are thermally cyclable, compliant actuators with compelling mechanical properties. The large and programmable deformation of LCE has led to numerous functional examinations spanning optics, medical devices, and robotics. A well-established method to prepare complex LCE actuators is to utilize surface-enforced photoalignment. Herein, a facile and scalable approach is reported to circumvent the physical limits of surface-enforced alignment (e.g., samples that are 50 µm or less) to amplify the achievable force output in LCE. Applying an approach termed direct layering, the thermomechanical response of LCE elements prepared with +1 disclination patterns in a range of compositions and thicknesses is contrasted. The design and preparation of +1 disclination patterns and arrays is explored to assess the contribution of sample geometry and overlap to deformation and force output. The methodology detailed in this contribution allows for the preparation of elements ≈1 mm in thickness that are capable of actuating large objects. Furthermore, the fabrication of these elements uniquely enables the realization of mechanical instabilities to hasten the actuation rate in response to thermal change and to enable leaping.

36 MATERIALS SCIENCE↗
DOE OSTI2022

The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors

We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of ℱ avg =99.93%. All of the schematics, firmware, and software are open-source.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1990

The design and proof of correctness of a fault-tolerant circuit

The flowing achievements are presented in view graph form: (1) a formal statement of interactive consistency conditions in the Boyer-Moore logic; (2) a formal statement of the oral messages (OM) algorithm in the Boyer-Moore logic; (3) a mechanically checked proof that OM satisfies the interactive consistency conditions; (4) a mechanically checked proof of the optimality result--no algorithm can tolerate fewer faults than OM yet still achieve interactive consistency; (5) the use of OM in a functional specification for a fault-tolerant device; (6) a formal description of the design of the device; (7) a mechanically checked proof that the device design satisfies the specification; and (8) an implementation of the design in programmable logic arrays.

Bevier, William R.↗
NASA NTRS2010

FPGA NEPP : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for re-programmable field programmable gate arrays (FPGAs). The FY09 task was divided into three efforts: 1. Device physics-based design modifications 2. Contention study of Xilinx Virtex-4 3. IDDQ study of Actel A54SX The FY09 NEPP FPGA study was organized into these three sections in recognition of the continued and increasing importance of FPGAs to NASA. FPGAs represent the state of the art in electronic components with millions and millions of transistors integrated into a single device. Modern NASA spacecraft design has dozens and dozens of FPGAs implemented onboard. FPGAs are used in critical command and data handling, instrument control and monitoring, and communications protocols, to name just a few. The reliability of FPGAs is fundamental to mission success for NASA.

Sheldon, Douglas↗
DOE OSTI2021

Architecture Of A Multi-channel Data Streaming Device With An Fpga As A Coprocessor

The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.

Nogiec, Jerzy M.↗
NASA NTRS1991

An electronic pan/tilt/zoom camera system

A camera system for omnidirectional image viewing applications that provides pan, tilt, zoom, and rotational orientation within a hemispherical field of view (FOV) using no moving parts was developed. The imaging device is based on the effect that from a fisheye lens, which produces a circular image of an entire hemispherical FOV, can be mathematically corrected using high speed electronic circuitry. An incoming fisheye image from any image acquisition source is captured in memory of the device, a transformation is performed for the viewing region of interest and viewing direction, and a corrected image is output as a video image signal for viewing, recording, or analysis. As a result, this device can accomplish the functions of pan, tilt, rotation, and zoom throughout a hemispherical FOV without the need for any mechanical mechanisms. A programmable transformation processor provides flexible control over viewing situations. Multiple images, each with different image magnifications and pan tilt rotation parameters, can be obtained from a single camera. The image transformation device can provide corrected images at frame rates compatible with RS-170 standard video equipment.

Zimmermann, Steve↗
DOE OSTI2023

Techniques for controlling charging and/or discharging of batteries using a tanks-in-series model

In some embodiments, a battery management system is provided. The battery management system comprises a connector for electrically coupling a battery to the battery management system, at least one sensor configured to detect a battery state, a programmable chip configured to control at least one of charging and discharging of the battery, and a controller device. The controller device is configured to receive at least one battery state from the at least one sensor; provide the at least one battery state as input to a tanks-in-series model that represents the battery; and provide at least one output of the tanks-in-series model to the programmable chip for controlling at least one of charging and discharging of the battery.

25 ENERGY STORAGE↗
DOE OSTI2021

Thermal hysteresis controlled reconfigurable MoS 2 nanomechanical resonators

Two-dimensional (2D) structures from layered materials have enabled a number of novel devices including resonant nanoelectromechanical systems (NEMS). 2D NEMS resonators are highly responsive to strain, allowing their resonance frequencies to be efficiently tuned over broad ranges, which is a feature difficult to attain in conventional micromachined resonators. In electrically configured and tuned devices, high external voltages are typically required to set and maintain different frequencies, limiting their applications. Here we experimentally demonstrate molybdenum disulfide (MoS 2 ) nanomechanical resonators that can be reconfigured between different frequency bands with zero maintaining voltage in a non-volatile fashion. By leveraging the thermal hysteresis in these 2D resonators, we use heating and cooling pulses to reconfigure the device frequency, with no external voltage required to maintain each frequency. Here, we further show that the frequency spacing between the bands can be tuned by the thermal pulse strength, offering full control over the programmable operation. Such reconfigurable MoS 2 resonators may provide an alternative pathway toward small-form-factor and low-power tunable devices in future reconfigurable radio-frequency circuits with multi-band capability.

42 ENGINEERING↗
DOE OSTI2024

sKokkos: Enabling Kokkos with Transparent Device Selection on Heterogeneous Systems using OpenACC

This paper presents a new feature to enable Kokkos with transparent device selection. For application developers, it is not easy toidentify which device is the most appropriate to use in a heterogeneous system, since this depends on the characteristics of both the application and the hardware. In Kokkos, a backend is associated with one specific programming model/hardware. Programmers decide which backend to use at compilation time. This new feature implemented on the OpenACC backend eliminates the burden of deciding which device to use, providing a highly productive programming solution for Kokkos applications. This work includes implementation details and a performance study conducted with a set of mini-benchmarks (i.e., AXPY and dot product), kernels (Lattice-Bolzmann method), and two mini-apps (LULESH and miniFE) on two heterogeneous systems with different hardware capabilities. This new Kokkos feature provides high accelerations of up to 35× thanks to automatic and transparent device selection.

Lee, Seyong↗