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At least 253 records · Page 14

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Hayes, P. J.↗

Active Flow Effectors for Noise and Separation Control

New flow effector technology for separation control and enhanced mixing is based upon shape memory alloy hybrid composite (SMAHC) technology. The technology allows for variable shape control of aircraft structures through actively deformable surfaces. The flow effectors are made by embedding shape memory alloy actuator material in a composite structure. When thermally actuated, the flow effector def1ects into or out of the flow in a prescribed manner to enhance mixing or induce separation for a variety of applications, including aeroacoustic noise reduction, drag reduction, and f1ight control. The active flow effectors were developed for noise reduction as an alternative to fixed-configuration effectors, such as static chevrons, that cannot be optimized for airframe installation effects or variable operating conditions and cannot be retracted for off-design or fail-safe conditions. Benefits include: Increased vehicle control, overall efficiency, and reduced noise throughout all f1ight regimes, Reduced flow noise, Reduced drag, Simplicity of design and fabrication, Simplicity of control through direct current stimulation, autonomous re sponse to environmental heating, fast re sponse, and a high degree of geometric stability. The concept involves embedding prestrained SMA actuators on one side of the chevron neutral axis in order to generate a thermal moment and def1ect the structure out of plane when heated. The force developed in the host structure during def1ection and the aerodynamic load is used for returning the structure to the retracted position. The chevron design is highly scalable and versatile, and easily affords active and/or autonomous (environmental) control. The technology offers wide-ranging market applications, including aerospace, automotive, and any application that requires flow separation or noise control.

Turner, Travis L.↗

Scalable low-loss cryogenic packaging of quantum memories in CMOS-foundry processed photonic chips

Optically linked solid-state quantum memories such as color centers in diamond are a promising platform for distributed quantum information processing and networking. Photonic integrated circuits (PICs) have emerged as a crucial enabling technology for these systems, integrating quantum memories with efficient electrical and optical interfaces in a compact and scalable platform. Packaging these hybrid chips into deployable modules while maintaining low optical loss and resiliency to temperature cycling is a central challenge to their practical use. We demonstrate a packaging method for PICs using surface grating couplers and angle-polished fiber arrays that is robust to temperature cycling, offers scalable channel count, applies to a wide variety of PIC platforms and wavelengths, and offers pathways to automated high-throughput packaging. Using this method, we show optically and electrically packaged quantum memory modules integrating all required qubit controls on chip, operating at millikelvin temperatures with <3 dB losses achievable from fiber to quantum memory for the TE 0 mode at a wavelength of 737 nm.

Bernson, Robert [Tyndall National Institute, Cork ↗

Stroboscope Controller for Imaging Helicopter Rotors

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Jensen, Scott↗

Thermomechanical Response of Shape Memory Alloy Hybrid Composites

This study examines the use of embedded shape memory alloy (SMA) actuators for adaptive control of the thermomechanical response of composite structures. A nonlinear thermomechanical model is presented for analyzing shape memory alloy hybrid composite (SMAHC) structures exposed to steady-state thermal and dynamic mechanical loads. Also presented are (1) fabrication procedures for SMAHC specimens, (2) characterization of the constituent materials for model quantification, (3) development of the test apparatus for conducting static and dynamic experiments on specimens with and without SMA, (4) discussion of the experimental results, and (5) validation of the analytical and numerical tools developed in the study. Excellent agreement is achieved between the predicted and measured SAMHC responses including thermal buckling, thermal post-buckling and dynamic response due to inertial loading. The validated model and thermomechanical analysis tools are used to demonstrate a variety of static and dynamic response behaviors including control of static (thermal buckling and post-buckling) and dynamic responses (vibration, sonic fatigue, and acoustic transmission). and SMAHC design considerations for these applications. SMAHCs are shown to have significant advantages over conventional response abatement approaches for vibration, sonic fatigue, and noise control.

Turner, Travis L.↗

Assessing the Effects of Momentary Priming on Memory Retention During an Interference Task

A memory aid, that used brief (33ms) presentations of previously learned information (target words), was assessed on its ability to reinforce memory for target words while the subject was performing an interference task. The interference task required subjects to learn new words and thus interfered with their memory of the target words. The brief presentation (momentary memory priming) was hypothesized to refresh the subjects memory of the target words. 143 subjects, in a within subject design, were given a 33ms presentation of the target memory words during the interference task in a treatment condition and a blank 33ms presentation in the control condition. The primary dependent measure, memory loss over the interference trial, was not significantly different between the two conditions. The memory prime did not appear to hinder the subjects performance on the interference task. This paper describes the experiment and the results along with suggestions for future research.

Schutte, Paul C.↗

Shape-Memory-Alloy Release Mechanism

Release-nut mechanism activated by electric current applied to shape-memory alloy. Separates attached objects quickly by remote control. Does not create hazard or cause damage. Shape-memory release-nut mechanism unaffected by moisture or vacuum. Requires sustained current lasting 5 seconds or longer, and insensitive to electromagnetic interference. Mechanism can be reused.

Mckinnis, Darin↗

Unveiling the nature of Ga-based chalcogenides for electrical switching selectors

Three-dimensional phase-change memory with stackable crossbar architecture is a promising technology to meet the urgent demands for high-density storage and rapid information processing in the era of explosive data growth. The performance depends strongly on the properties of ovonic threshold switching (OTS) selectors, which control the on/off states of memory units. Amorphous GaS serves as an outstanding OTS material, distinguished by its sizable mobility gap and high crystallization temperature, while the underlying mechanism continues to be inadequately comprehended. Here, in this work, we systematically studied the structural and electronic properties of amorphous Ga-X (X = S/Se/Te) using first-principles calculations. The results show that Ga atoms adopt tetrahedral motifs, while S/Se/Te atoms predominantly exhibit the structure of a distorted triangular pyramid. This structural arrangement is ascribed to the substantial dative bonds formed by the lone-pair electrons of the anions and the vacant sp3 orbitals around Ga atoms. Large mobility gaps (e.g., GaS: 2.43 eV, GaSe: 1.76 eV, GaTe: 1.26 eV) and distinct mid-gap states (e.g., ∼0.66 eV above valence band tail) ensure that these three chalcogenide glasses can be switched on under an external electric field while effectively suppressing leakage current without a bias, and the defect electronic states originate from short, robust Ga-Ga bonds due to the formation of distorted chain-like local structures. Our research elucidates the mechanisms of amorphous Ga-X as OTS materials, enriching the spectrum of electrical switching selectors by incorporating III-VI chalcogenides. This inclusion offers novel opportunities for the refinement and optimization of high-density integrated memory systems.

36 MATERIALS SCIENCE↗

Persistence length regulates emergent dynamics in active roller ensembles

Active colloidal fluids, biological and synthetic, often demonstrate complex self-organization and the emergence of collective behavior. Spontaneous formation of multiple vortices has been recently observed in a variety of active matter systems, however, the generation and tunability of the active vortices not controlled by geometrical confinement remain challenging. Here, we exploit the persistence length of individual particles in ensembles of active rollers to tune the formation of vortices and to orchestrate their characteristic sizes. We use two systems and employ two different approaches exploiting shape anisotropy or polarization memory of individual units for control of the persistence length. We characterize the dynamics of emergent multi-vortex states and reveal a direct link between the behavior of the persistence length and properties of the emergent vortices. We further demonstrate common features between the two systems including anti-ferromagnetic ordering of the neighboring vortices and active turbulent behavior with a characteristic energy cascade in the particles velocity field energy spectra. Finally, our findings provide insights into the onset of spatiotemporal coherence in active roller systems and suggest a control knob for manipulation of dynamic self-assembly in active colloidal ensembles.

42 ENGINEERING↗

GOAT. jl

SF-23-008 This project is a Julia implementation of the Gradient Optimization of Analytic conTrols (GOAT) optimal control methodology. It integrates with other packages in Julia's ecosystem to provide memory-efficient, parallelized solutions to quantum optimal control tasks. A prototype implementation of some of these algorithms was initially developed and funded by the ASCR Early Career Research Award program under PI Travis Humble at Oak Ridge National Laboratory. The current version was funded under the ASCR AIDE-QC Program under PI Paul Hovland. The current package to be released has a novel implementation, syntax, and structure making it substantially different than the original prototype (which was not released under copyright to the best of my knowledge).

KAIRYS, PAUL↗

Computerized monitoring and control of experiments in space

The computer subsystem of the Villanova University GAS (Get Away Special) experiment apparatus is discussed. The function of the computer subsystem is to provide data acquisition and control system support to the experiments. The computer subsystem will provide high availability, low power consumption and highly reliable data retention. The general layout of the subsystem provides for redundant processing units, control modules, and multiple data acquisition modules. Each of the two redundant processing units will be composed of a microprocessor, control logic, PROM, RAM, non-volitile memory, timers, self-check logic and data ports to the data acquisition and control modules. One unit will control the experiment while the other shadows the primary unit operation. The data acquisition module gathers data from the experiment. The data is transfered to the processing unit in digital form. The control module validates the data, decodes it and executes the command.

Janisch, Thomas V.↗

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Barrett, W. J.↗

Fractal fluctuations in cardiac time series

Human heart rate, controlled by complex feedback mechanisms, is a vital index of systematic circulation. However, it has been shown that beat-to-beat values of heart rate fluctuate continually over a wide range of time scales. Herein we use the relative dispersion, the ratio of the standard deviation to the mean, to show, by systematically aggregating the data, that the correlation in the beat-to-beat cardiac time series is a modulated inverse power law. This scaling property indicates the existence of long-time memory in the underlying cardiac control process and supports the conclusion that heart rate variability is a temporal fractal. We argue that the cardiac control system has allometric properties that enable it to respond to a dynamical environment through scaling.

NASA Discipline Cardiopulmonary↗

Working and strategic memory deficits in schizophrenia

Working memory and its contribution to performance on strategic memory tests in schizophrenia were studied. Patients (n = 18) and control participants (n = 15), all men, received tests of immediate memory (forward digit span), working memory (listening, computation, and backward digit span), and long-term strategic (free recall, temporal order, and self-ordered pointing) and nonstrategic (recognition) memory. Schizophrenia patients performed worse on all tests. Education, verbal intelligence, and immediate memory capacity did not account for deficits in working memory in schizophrenia patients. Reduced working memory capacity accounted for group differences in strategic memory but not in recognition memory. Working memory impairment may be central to the profile of impaired cognitive performance in schizophrenia and is consistent with hypothesized frontal lobe dysfunction associated with this disease. Additional medial-temporal dysfunction may account for the recognition memory deficit.

Memory Disorders/etiology/physiopathology↗

Design and implementation of a medium speed communications interface and protocol for a low cost, refreshed display computer

The design and implementation of hardware and software systems involved in using a 40,000 bit/second communication line as the connecting link between an IMLAC PDS 1-D display computer and a Univac 1108 computer system were described. The IMLAC consists of two independent processors sharing a common memory. The display processor generates the deflection and beam control currents as it interprets a program contained in the memory; the minicomputer has a general instruction set and is responsible for starting and stopping the display processor and for communicating with the outside world through the keyboard, teletype, light pen, and communication line. The processing time associated with each data byte was minimized by designing the input and output processes as finite state machines which automatically sequence from each state to the next. Several tests of the communication link and the IMLAC software were made using a special low capacity computer grade cable between the IMLAC and the Univac.

Phyne, J. R.↗

Fast Initialization of Bubble-Memory Systems

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

Looney, K. T.↗

Cooperative Data Sharing: Simple Support for Clusters of SMP Nodes

Libraries like PVM and MPI send typed messages to allow for heterogeneous cluster computing. Lower-level libraries, such as GAM, provide more efficient access to communication by removing the need to copy messages between the interface and user space in some cases. still lower-level interfaces, such as UNET, get right down to the hardware level to provide maximum performance. However, these are all still interfaces for passing messages from one process to another, and have limited utility in a shared-memory environment, due primarily to the fact that message passing is just another term for copying. This drawback is made more pertinent by today's hybrid architectures (e.g. clusters of SMPs), where it is difficult to know beforehand whether two communicating processes will share memory. As a result, even portable language tools (like HPF compilers) must either map all interprocess communication, into message passing with the accompanying performance degradation in shared memory environments, or they must check each communication at run-time and implement the shared-memory case separately for efficiency. Cooperative Data Sharing (CDS) is a single user-level API which abstracts all communication between processes into the sharing and access coordination of memory regions, in a model which might be described as "distributed shared messages" or "large-grain distributed shared memory". As a result, the user programs to a simple latency-tolerant abstract communication specification which can be mapped efficiently to either a shared-memory or message-passing based run-time system, depending upon the available architecture. Unlike some distributed shared memory interfaces, the user still has complete control over the assignment of data to processors, the forwarding of data to its next likely destination, and the queuing of data until it is needed, so even the relatively high latency present in clusters can be accomodated. CDS does not require special use of an MMU, which can add overhead to some DSM systems, and does not require an SPMD programming model. unlike some message-passing interfaces, CDS allows the user to implement efficient demand-driven applications where processes must "fight" over data, and does not perform copying if processes share memory and do not attempt concurrent writes. CDS also supports heterogeneous computing, dynamic process creation, handlers, and a very simple thread-arbitration mechanism. Additional support for array subsections is currently being considered. The CDS1 API, which forms the kernel of CDS, is built primarily upon only 2 communication primitives, one process initiation primitive, and some data translation (and marshalling) routines, memory allocation routines, and priority control routines. The entire current collection of 28 routines provides enough functionality to implement most (or all) of MPI 1 and 2, which has a much larger interface consisting of hundreds of routines. still, the API is small enough to consider integrating into standard os interfaces for handling inter-process communication in a network-independent way. This approach would also help to solve many of the problems plaguing other higher-level standards such as MPI and PVM which must, in some cases, "play OS" to adequately address progress and process control issues. The CDS2 API, a higher level of interface roughly equivalent in functionality to MPI and to be built entirely upon CDS1, is still being designed. It is intended to add support for the equivalent of communicators, reduction and other collective operations, process topologies, additional support for process creation, and some automatic memory management. CDS2 will not exactly match MPI, because the copy-free semantics of communication from CDS1 will be supported. CDS2 application programs will be free to carefully also use CDS1. CDS1 has been implemented on networks of workstations running unmodified Unix-based operating systems, using UDP/IP and vendor-supplied high- performance locks. Although its inter-node performance is currently unimpressive due to rudimentary implementation technique, it even now outperforms highly-optimized MPI implementation on intra-node communication due to its support for non-copy communication. The similarity of the CDS1 architecture to that of other projects such as UNET and TRAP suggests that the inter-node performance can be increased significantly to surpass MPI or PVM, and it may be possible to migrate some of its functionality to communication controllers.

DiNucci, David C.↗