Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “hardware accelerators”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Solid Propulsion Systems, Subsystems, and Components Service Life Extension

The service life extension of solid propulsion systems, subsystems, and components will be discussed based on the service life extension of the Space Transportation System Reusable Solid Rocket Motor (RSRM) and Booster Separation Motors (BSM). The RSRM is certified for an age life of five years. In the aftermath of the Columbia accident there were a number of motors that were approaching the end of their five year service life certification. The RSRM Project initiated an assessment to determine if the service life of these motors could be extended. With the advent of the Constellation Program, a flight test was proposed that would utilize one of the RSRMs which had been returned from the launch site due to the expiration of its five year service life certification and twelve surplus Chemical Systems Division BSMs which had exceeded their eight year service life. The RSRM age life tracking philosophy which establishes when the clock starts for age life tracking will be described. The role of the following activities in service life extension will be discussed: subscale testing, accelerated aging, dissecting full scale aged hardware, static testing full scale aged motors, data mining industry data, and using the fleet leader approach. The service life certification and extension of the BSMs will also be presented.

Hundley, Nedra H.↗
NASA NTRS2011

IONAC-Lite

The Interplanetary Overlay Net - working Protocol Accelerator (IONAC) described previously in The Inter - planetary Overlay Networking Protocol Accelerator (NPO-45584), NASA Tech Briefs, Vol. 32, No. 10, (October 2008) p. 106 (http://www.techbriefs.com/component/ content/article/3317) provides functions that implement the Delay Tolerant Networking (DTN) bundle protocol. New missions that require high-speed downlink-only use of DTN can now be accommodated by the unidirectional IONAC-Lite to support high data rate downlink mission applications. Due to constrained energy resources, a conventional software implementation of the DTN protocol can provide only limited throughput for any given reasonable energy consumption rate. The IONAC-Lite DTN Protocol Accelerator is able to reduce this energy consumption by an order of magnitude and increase the throughput capability by two orders of magnitude. In addition, a conventional DTN implementation requires a bundle database with a considerable storage requirement. In very high downlink datarate missions such as near-Earth radar science missions, the storage space utilization needs to be maximized for science data and minimized for communications protocol-related storage needs. The IONAC-Lite DTN Protocol Accelerator is implemented in a reconfigurable hardware device to accomplish exactly what s needed for high-throughput DTN downlink-only scenarios. The following are salient features of the IONAC-Lite implementation: An implementation of the Bundle Protocol for an environment that requires a very high rate bundle egress data rate. The C&DH (command and data handling) subsystem is also expected to be very constrained so the interaction with the C&DH processor and the temporary storage are minimized. Fully pipelined design so that bundle processing database is not required. Implements a lookup table-based approach to eliminate multi-pass processing requirement imposed by the Bundle Protocol header s length field structure and the SDNV (self-delimiting numeric value) data field formatting. 8-bit parallel datapath to support high data-rate missions. Reduced resource utilization implementation for missions that do not require custody transfer features. There was no known implementation of the DTN protocol in a field programmable gate array (FPGA) device prior to the current implementation. The combination of energy and performance optimization that embodies this design makes the work novel.

Torgerson, Jordan L.↗
NASA NTRS2013

Rocket Sled Propelled Testing of a Supersonic Inflatable Aerodynamic Decelerator

Decelerators (IADs) have traditionally been tested in wind tunnels. As the limitations of these test facilities are reached, other avenues must be pursued. The IAD being tested is a Supersonic IAD (SIAD), which attaches just aft of the heatshield around the perimeter of an entry body. This 'attached torus' SIAD is meant to improve the accuracy of landing for robotic class missions to Mars and allow for potentially increased payloads. The SIAD Design Verification (SDV) test aims to qualify the SIAD by applying a targeted aerodynamic load to the vehicle. While many test architectures were researched, a rocket sled track was ultimately chosen to be the most cost effective way to achieve the desired dynamic pressures. The Supersonic Naval Ordnance Research Track (SNORT) at the Naval Air Warfare Center Weapons Division (NAWCWD) China Lake is a four mile test track, traditionally used for warhead and ejection seat testing. Prior to SDV, inflatable drag bodies have been tested on this particular track. Teams at Jet Propulsion Laboratory (JPL) and NAWCWD collaborate together to design and fabricate one of the largest sleds ever built. The SDV sled is comprised of three individual sleds: a Pusher Sled which holds the solid booster rockets, an Item Sled which supports the test vehicle, and a Camera Sled that is pushed in front for in-situ footage and measurements. The JPL-designed Test Vehicle has a full-scale heatshield shape and contains all instrumentation and inflation systems necessary to inflate and test a SIAD. The first campaign that is run at SNORT tested all hardware and instrumentation before the SIAD was ready to be tested. For each of the three tests in this campaign, the number of rockets and top speed was increased and the data analyzed to ensure the hardware is safe at the necessary accelerations and aerodynamic loads.

Supersonic Inflatable Aerodynamic Decelerators (SI↗
DOE OSTI2022

VWC-BERT: Scaling Vulnerability–Weakness–Exploit Mapping on Modern AI Accelerators

Defending cybersystems needs accurate mapping of software and hardware vulnerabilities to generalized descriptions of weaknesses, and weaknesses to exploits. These mappings enable cyber defenders to build plans for effective defense and assessment of potential risks to a cybersystem. With close to 170k vulnerabilities, manual mapping is not a feasible option. However, automated mapping is challenging due to limited training data, computational intractability, and limitations in computational natural language processing. Tools based on breakthroughs in Transformer-based language models have been demonstrated to classify vulnerabilities with high accuracy. We make three key contributions in this paper: (1) We present a new framework, \VWCBERT, that augments the Transformer-based hierarchical multi-class classification framework of Das et al. (\textsc{V2W-BERT}) with the ability to map weaknesses to exploits. (2) We implement \VWCBERT~ on modern AI accelerator platforms using two data parallel techniques for the pre-training phase and demonstrate nearly linear speedups across NVIDIA and Graphcore accelerator platforms. We observe nearly linear speedups for up to 16 V100 and 8 A100 GPUs, and about 3.4$\times$ speedup for A100 relative to V100 GPUs. We also observe excellent speedups on Graphcore, with $5.7\times$ speedup on 128 IPUs relative to 16 IPUs. Enabled by scaling, we also demonstrate higher accuracy using a larger language model, RoBERTa-Large. We show up to 87\% accuracy for strict and up to 98\% accuracy for relaxed classification. (3) We develop a novel parallel link manager for the link prediction phase and demonstrate up to 21$\times$ speedup with 16 V100 GPUs relative to one V100 GPU, and thus reducing the runtime from 2.5 hours to 10 minutes. We believe that generalizability and scalability of \VWCBERT~ will benefit both the theoretical development and practical deployment of novel cyberdefense solutions and vulnerability classification.

Das, Siddhartha Shankar↗
NASA NTRS1995

Computational System For Rapid CFD Analysis In Engineering

Computational system comprising modular hardware and software sub-systems developed to accelerate and facilitate use of techniques of computational fluid dynamics (CFD) in engineering environment. Addresses integration of all aspects of CFD analysis process, including definition of hardware surfaces, generation of computational grids, CFD flow solution, and postprocessing. Incorporates interfaces for integration of all hardware and software tools needed to perform complete CFD analysis. Includes tools for efficient definition of flow geometry, generation of computational grids, computation of flows on grids, and postprocessing of flow data. System accepts geometric input from any of three basic sources: computer-aided design (CAD), computer-aided engineering (CAE), or definition by user.

Barson, Steven L.↗
NASA NTRS1999

Measurement and Data Distribution for Microgravity Accelerations on the International Space Station

Two accelerometer systems will be available on the International Space Station to support microgravity payloads with information about the quasi-steady and vibratory acceleration environment of the research facilities. The Microgravity Acceleration Measurement System will record contributions to the quasi-steady microgravity environment, including the influences of aerodynamic drag, vehicle rotation, and venting effects. The Space Acceleration Measurement System-II will measure vibratory disturbances on-board due to vehicle, crew, and equipment disturbances. Due to the dynamic nature of the microgravity environment and its potential to influence sensitive experiments, NASA's Principal Investigator Microgravity Services project has initiated a plan through which the data from these instruments will be distributed to researchers in a timely and meaningful fashion. Beyond the obvious benefit of correlation between accelerations and the scientific phenomena being studied, such information is also useful for hardware developers who can gain qualitative and quantitative feedback about their facility acceleration output to station.

McPherson, Kevin↗
NASA NTRS2000

A Linux Workstation for High Performance Graphics

The primary goal of this effort was to provide a low-cost method of obtaining high-performance 3-D graphics using an industry standard library (OpenGL) on PC class computers. Previously, users interested in doing substantial visualization or graphical manipulation were constrained to using specialized, custom hardware most often found in computers from Silicon Graphics (SGI). We provided an alternative to expensive SGI hardware by taking advantage of third-party, 3-D graphics accelerators that have now become available at very affordable prices. To make use of this hardware our goal was to provide a free, redistributable, and fully-compatible OpenGL work-alike library so that existing bodies of code could simply be recompiled. for PC class machines running a free version of Unix. This should allow substantial cost savings while greatly expanding the population of people with access to a serious graphics development and viewing environment. This should offer a means for NASA to provide a spectrum of graphics performance to its scientists, supplying high-end specialized SGI hardware for high-performance visualization while fulfilling the requirements of medium and lower performance applications with generic, off-the-shelf components and still maintaining compatibility between the two.

Geist, Robert↗
DOE OSTI2022

Strategy for Modernizing a 40-Year-Old Accelerator Control System

Modernizing the Fermilab accelerator control system is essential to future operations of the laboratory's accelerator complex. The existing control system has evolved over four decades and uses hardware that is no longer available and software that uses obsolete frameworks. The Accelerator Controls Operations Research Network (ACORN) Project will modernize the control system and replace end-of-life power supplies to enable future accelerator complex operations with megawatt particle beams. The project team is evaluating three design concepts, and the future deployment of artificial intelligence capabilities for accelerator operations is an important consideration. An overview of the ACORN Project will be presented, including R&D used for evaluating the conceptual designs in the context of requirements for future accelerator operations.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

Introduction and Status of Fermilab's ACORN Project

Modernizing the Fermilab accelerator control system is essential to future operations of the laboratory's accelerator complex. The existing control system has evolved over four decades and uses hardware that is no longer available and software that uses obsolete frameworks. The Accelerator Controls Operations Research Network (ACORN) Project will modernize the control system and replace end-of-life power supplies to enable future accelerator complex operations with megawatt particle beams. An overview of the ACORN Project and a summary of recent research and development activities will be presented.

43 PARTICLE ACCELERATORS↗
DOE OSTI2021

Binary Complex Neural Network Acceleration on FPGA

Being able to learn from complex data with phase information is imperative for many signal processing applications. Today’s real-valued deep neural networks (DNNs) have shown efficiency in latent information analysis but fall short when applied to the complex domain. Deep complex networks (DCN) , in contrast, can learn from complex data, but have high computational costs; therefore, they cannot satisfy the instant decision making requirements of many deployable systems dealing with short observations or short signal bursts. Recent, Binarized Complex Neural Network (BCNN), which integrates DCNs with binarized neural networks (BNN), shows great potential in classifying complex data in real-time. In this paper, we propose a structural pruning based accelerator of BCNN, which is able to provide more than 5000 frames/s inference throughput on edge devices. The high performance comes from both the algorithm and hardware sides. On the algorithm side, we conduct structural pruning to the original BCNN models and obtain 20 × pruning rates with negligible accuracy loss; on the hardware side, we propose a novel 2D convolution operation accelerator for the binary complex neural network. Experimental results show that the proposed design works with over 90% utilization and is able to achieve the inference throughput of 5882 frames/s and 4938 frames/s for complex NIN-Net and ResNet-18 using CIFAR-10 dataset and Alveo U280 Board.

Peng, Hongwu↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

The SODA Approach: Leveraging High-Level Synthesis for Hardware/Software Co-design and Hardware Specialization: Invited

Novel "converged" applications combine phases of scientific simulation with data analysis and machine learning. Each computational phase can benefit from specialized accelerators. However, algorithms evolve so quickly that mapping them on existing accelerators is suboptimal or even impossible. This paper presents the SODA (Software Defined Accelerators) framework, a modular, multi-level, open-source, no-human-in-the-loop, hardware synthesizer that enables end-to-end generation of specialized accelerators. SODA is composed of SODA-Opt, a high-level frontend developed in MLIR that interfaces with domain-specific programming frameworks and allows performing system level design, and Bambu, a state-of-the-art high-level synthesis engine that can target different device technologies. The framework implements design space exploration as compiler optimization passes. We show how the modular, yet tight, integration of the high-level optimizer and lower-level HLS tools enables the generation of accelerators optimized for the computational patterns of converged applications. We then discuss some of the research opportunities that such a framework allows, including system-level design, profile driven optimization, and supporting new optimization metrics.

Bohm Agostini, Nicolas↗
NASA NTRS2006

Acceleration of Stereo Correlation in Verilog

To speed up vision processing in low speed, low power devices, embedding FPGA hardware is becoming an effective way to add processing capability. FPGAs offer the ability to flexibly add parallel and/or deeply pipelined computation to embedded processors without adding significantly to the mass and power requirements of an embedded system. This paper will discuss the JPL stereo vision system, and describe how a portion of that system was accelerated by using custom FPGA hardware to process the computationally intensive portions of JPL stereo. The architecture described takes full advantage of the ability of an FPGA to use many small computation elements in parallel. This resulted in a 16 times speedup in real hardware over using a simple linear processor to compute image correlation and disparity.

machine vision↗
DOE OSTI2023

Quantum computing for fusion energy science applications

This is a review of recent research exploring and extending present-day quantum computing capabilities for fusion energy science applications. We begin with a brief tutorial on both ideal and open quantum dynamics, universal quantum computation, and quantum algorithms. Then, we explore the topic of using quantum computers to simulate both linear and nonlinear dynamics in greater detail. Because quantum computers can only efficiently perform linear operations on the quantum state, it is challenging to perform nonlinear operations that are generically required to describe the nonlinear differential equations of interest. In this work, we extend previous results on embedding nonlinear systems within linear systems by explicitly deriving the connection between the Koopman evolution operator, the Perron–Frobenius evolution operator, and the Koopman–von Neumann evolution (KvN) operator. We also explicitly derive the connection between the Koopman and Carleman approaches to embedding. Extension of the KvN framework to the complex-analytic setting relevant to Carleman embedding, and the proof that different choices of complex analytic reproducing kernel Hilbert spaces depend on the choice of Hilbert space metric are covered in the appendixes. Finally, we conclude with a review of recent quantum hardware implementations of algorithms on present-day quantum hardware platforms that may one day be accelerated through Hamiltonian simulation. We discuss the simulation of toy models of wave–particle interactions through the simulation of quantum maps and of wave–wave interactions important in nonlinear plasma dynamics.

Joseph, I. (ORCID:0000000255400840)↗
DOE OSTI2025

Surrogate optimization of variational quantum circuits

Variational quantum eigensolvers are touted as a near-term algorithm capable of impacting many applications. However, the potential has not yet been realized, with few claims of quantum advantage and high resource estimates, especially due to the need for optimization in the presence of noise. Finding algorithms and methods to improve convergence is important to accelerate the capabilities of near-term hardware for VQE or more broad applications of hybrid methods in which optimization is required. To this goal, we look to use modern approaches developed in circuit simulations and stochastic classical optimization, which can be combined to form a surrogate optimization approach to quantum circuits. Using an approximate (classical CPU/GPU) state vector simulator as a surrogate model, we efficiently calculate an approximate Hessian, passed as an input for a quantum processing unit or exact circuit simulator. This method will lend itself well to parallelization across quantum processing units. We demonstrate the capabilities of such an approach with and without sampling noise and a proof-of-principle demonstration on a quantum processing unit utilizing 40 qubits.

Gustafson, Erik J. [RIACS, Mtn. View] (ORCID:00000↗
DOE OSTI2022

Scalable Second Order Optimization for Machine Learning

Many machine learning (ML) training tasks are essentially optimization processes that would at first glance appear eminently parallelizable and scalable. However, effective acceleration of these tasks with scalable parallel hardware has proven to be elusive. While standard methods for machine learning, e.g., stochastic gradient descent (SGD) for DNNs, tend to be resource efficient, they appear to be fundamentally sequential in nature.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1978

Platform motion for fighter simulations

The reported investigation is concerned with aspects of 'realistic' cue generation and evaluation. 'Realistic' cues are defined to mean cues that are representative of an aircraft, that are of sufficient magnitude to be sensed, that are in the proper direction arriving at the proper time, and yet that are within the presentation capabilities of the washout/synergistic platform system. Attention is given to the aircraft mathematical model, computer implementation, cockpit hardware, visual display, the motion system, vertical acceleration, longitudinal acceleration and pitch rate, and lateral acceleration and roll rate. The motion cues for fighter aircraft produced by Langley nonlinear adaptive washout/synergistic motion base system are found to be unacceptable in the roll axis representation. However, a method for producing potentially realistic roll cues is identified.

Parrish, R. V.↗
NASA NTRS2003

Advanced Data Acquisition Systems

Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.

Perotti, J.↗