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A reliable and economical new transmission code is presented with the following properties: zero dc content, baseband bandwidth conservation, self-clocking capability, and data-rate-transparent decoding and synchronization. Simple encoder/decoder and clock extractor circuits are given. The code is demonstrated in a wavelength-multiplexed fiber-optic communication system.
Problems of redundancy and correlation avoided. ORTHO computer program eliminates effect of clock errors in differential solutions for positions of users of Global Positioning System (GPS). Main application, elimination of clock errors in tracking system based on GPS. Written in FORTRAN 77.
A formal specification and mechanically assisted verification of the interactive convergence clock synchronization algorithm of Lamport and Melliar-Smith is described. Several technical flaws in the analysis given by Lamport and Melliar-Smith were discovered, even though their presentation is unusally precise and detailed. It seems that these flaws were not detected by informal peer scrutiny. The flaws are discussed and a revised presentation of the analysis is given that not only corrects the flaws but is also more precise and easier to follow. Some of the corrections to the flaws require slight modifications to the original assumptions underlying the algorithm and to the constraints on its parameters, and thus change the external specifications of the algorithm. The formal analysis of the interactive convergence clock synchronization algorithm was performed using the Enhanced Hierarchical Development Methodology (EHDM) formal specification and verification environment. This application of EHDM provides a demonstration of some of the capabilities of the system.
Some interim results from the environmental testing program to evaluate the Engineering Design Model (EDM) of the EG and G Spaceborne Rubidium Clock are presented. This effort is in support of the Global Positioning System (GPS) BLOCK IIR program and is intended to characterize the performance of EG and G design for BLOCK IIR satellite applications. Two EG and G EDM units are currently under test at NRL's Clock Test Facility to measure the long-term frequency stability, drift, and frequency versus temperature characteristics.
Existing fault-tolerant clock synchronization algorithms are compared and contrasted. These include the following: software synchronization algorithms, such as convergence-averaging, convergence-nonaveraging, and consistency algorithms, as well as probabilistic synchronization; hardware synchronization algorithms; and hybrid synchronization. The worst-case clock skews guaranteed by representative algorithms are compared, along with other important aspects such as time, message, and cost overhead imposed by the algorithms. More recent developments such as hardware-assisted software synchronization and algorithms for synchronizing large, partially connected distributed systems are especially emphasized.
Magnetic reconnection between the IMF and the geomagnetic field is thought to play a major role in the transfer of solar wind momentum and energy to the magnetosphere. Both analytic modeling and analysis of geophysical data have shown that this coupling process should be a sensitive function of the clock angle of the IMF. Results are presented from a three-dimensional, MHD, global numerical simulation code for the reconnection voltage between the closed geomagnetic field and the IMF as a function of the IMF clock angle. These results are consistent with a sin(theta/2) functional behavior.
A printed circuit board which will provide external clocks and precisely measure the time at which events take place was designed for the Bristol University Gas Spectrometer (BUGS). The board, which was designed to interface both mechanically and electrically to the Computer Automated Measurement and Control (CAMAC) system, has been named the BUGS system clock control. The board's design and use are described.
Schneider demonstrates that many fault tolerant clock synchronization algorithms can be represented as refinements of a single proven correct paradigm. Shankar provides mechanical proof that Schneider's schema achieves Byzantine fault tolerant clock synchronization provided that 11 constraints are satisfied. Some of the constraints are assumptions about physical properties of the system and cannot be established formally. Proofs are given that the fault tolerant midpoint convergence function satisfies three of the constraints. A hardware design is presented, implementing the fault tolerant midpoint function, which is shown to satisfy the remaining constraints. The synchronization circuit will recover completely from transient faults provided the maximum fault assumption is not violated. The initialization protocol for the circuit also provides a recovery mechanism from total system failure caused by correlated transient faults.
In 1987, Schneider presented a general paradigm that provides a single proof of a number of fault tolerant clock synchronization algorithms. His proof was subsequently subjected to the rigor of mechanical verification by Shankar. However, both Schneider and Shankar assumed a condition Shankar refers to as a bounded delay. This condition states that the elapsed time between synchronization events (i.e., the time that the local process applies an adjustment to its logical clock) is bounded. This property is really a result of the algorithm and should not be assumed in a proof of correctness. This paper remedies this by providing a proof of this property in the context of the general paradigm proposed by Schneider. The argument given is a generalization of Welch and Lynch's proof of a related property for their algorithm.
Operation of deep space missions requires stable frequency references and clocks to perform several mission critical functions. These references are used in generating the telecommunication links to maintain communications between earth and spacecraft, in generating accurate doppler, range, and very long baseline interferometry (VLBI) observables for determining the spacecraft's time varying position, and to generate on-board timing information for clocking out timed commands and time tagging instrument data. In addition, science applications exist, particularly those utilizing radio instrumentation, which can require additional functions and levels of performance. The design necessary to support these functions affects both the spacecraft and the ground tracking stations. This paper provides a brief description of these functions and some of the key requirements needed to support them.
Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.
The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.
Displays including images of alarm clocks illustrate temporal statuses of multiple events. MCLK is customizable clock-display computer program with Motif user interface. Used to keep track of such multiple "milestone" events as those occurring during countdowns in spacecraft launches, and alerts user when event time reached. In addition, program displays time from several time zones. Real time measured in Coordinated Universal Time. Written in C language.
Evidence indicates that the 154-day periodicity in solar activity may be part of a complex of periodicities that are approximate multiples of 25.8 d, which suggests that the sun contains a 'clock' with frequency in the range 440-463 nHz. To search for evidence of this clock, the daily Greenwich sunspot areas and daily Zurich sunspot numbers have been Fourier-analyzed. The Zurich data show a strong peak that may clearly be identified with the fundamental frequency, while the Greenwich data show a peak that may be the harmonic of the fundamental frequency. A model is discussed which provides a kinematical interpretation of the sunspot spectrum.
Several methods for characterizing the performance of clocks with special emphasis on using calibration information that is acquired via an unreliable or noisy channel is discussed. Time-domain variance estimators and frequency-domain techniques such as cross-spectral analysis are discussed. Each of these methods has advantages and limitations that will be illustrated using data obtained via GPS, ACTS, and other methods. No one technique will be optimum for all of these analyses, and some of these problems cannot be completely characterized by any of the techniques discussed. The inverse problem of communicating frequency and time corrections to a real-time steered clock are also discussed. Methods were developed to mitigate the disastrous problems of data corruption and loss of computer control.
Although in accuracy parameters GLONASS is correlated with GPS, using GLONASS signals for high-precision clock synchronization was, up to the recent time, of limited utility due to the lack of specialized time receivers. In order to improve this situation, in late 1992 the Russian Institute of Radionavigation and Time (RMT) began to develop a GLONASS time receiver using as a basis the airborne ASN-16 receiver. This paper presents results of estimating user clock synchronization accuracy via GLONASS signals using ASN-16 receiver in the direct synchronization and common-view modes.
The weighting scheme for the cesium clocks and hydrogen masers constituting the USNO timing ensemble is reexamined from an empirical standpoint of maximizing both frequency accuracy and timescale uniformity. The utility of a sliding-weight relation between the masers and the cesiums is reaffirmed, but improvement is found if one incorporates inverse Allan variances for sampling times of 12 and 6 hours for the cesiums and masers, respectively, with some dependence on clock model.
This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.