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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Deep Learning for Spectral Filling in Radio Frequency Applications

Due to the Internet of Things (IoT) proliferation, Radio Frequency (RF) channels are increasingly congested with new kinds of devices, which carry unique and diverse communication needs. This poses complex challenges in modern digital communications, and calls for the development of technological innovations that (i) optimize capacity (bitrate) in limited bandwidth environments, (ii) integrate cooperatively with already-deployed RF protocols, and (iii) are adaptive to the ever-changing demands in modern digital communications. In this paper we present methods for applying deep neural networks for spectral filling. Given an RF channel transmitting digital messages with a pre-established modulation scheme, we automatically learn novel modulation schemes for sending extra information, in the form of additional messages, “around” the fixed-modulation signals (i.e., without interfering with them). In so doing, we effectively increase channel capacity without increasing bandwidth. We further demonstrate the ability to generate signals that closely resemble the original modulations, such that the presence of extra messages is undetectable to third-party listeners. We present three computational experiments demonstrating the efficacy of our methods, and conclude by discussing the implications of our results for modern RF applications.

Setzler, Matthew D.↗
DOE OSTI2025

Piezo-Antenna: An Electromagnetic-Ultrasonic Data Transfer System

Electronic systems contained within sealed metallic enclosures, such as nuclear waste containers where wire penetration is not an option, require a through-wall data transfer technology to communicate. One such technology utilizes piezoelectric ultrasonic transducers to communicate through the barrier using elastic waves. Currently demonstrated ultrasonic through-wall data communication techniques have relied on having a direct interface with the ultrasonic transducers on either side. Here, this work studies the coupling of an antenna to such an ultrasonic communication system. A computationally efficient model of a piezobarrier ultrasonic communication system and antenna using a simplified antenna model and a transfer matrix piezobarrier model is utilized to perform a representative parameter space search. The system efficiency and bandwidth trends are shown for the system parameters as well as operating frequency. The tradeoff between efficiency and bandwidth is also presented. A system configuration within the parameter space is fabricated and demonstrated to achieve a data rate of up to 100 kb/s.

Antenna↗
DOE OSTI2026

Bistable Optical Semiconductor Switching Based on C-Doped GaN

Highly resistive gallium nitride (GaN) is an essential material for power optoelectronic applications. While carbon doping is widely used to achieve semi-insulating properties in GaN, the persistent photoconductivity (PPC) arising from deep-level defect traps remains a major obstacle for high-speed power switching. This study demonstrates a novel approach: leveraging the ultrahigh photoresponsivity of GaN:C (up to 2.1 A ⋅ cm/W ⋅ kV, surpassing alternatives such as GaN:Fe) and employing defect-selective optical control to effectively quench the PPC. By synchronizing a short infrared (1064 nm) quenching pulse with UV (385 nm) excitation in an epitaxially grown GaN:C layer on a heavily doped n-type GaN substrate, we achieve a dramatic reduction in photocurrent fall time by approximately 293× (from 470 to 1.6 μ s), increasing modulation bandwidth from 745 Hz to nearly 218 kHz. Here, this advancement not only establishes a new pathway for controlling PPC in GaN:C but also enables the practical integration of GaN:C in fast power switching devices. Enhanced modulation bandwidth, along with GaN:C excellent photoresponsivity, makes it a promising candidate for optically controlled high-voltage, high-power electronic systems, such as photoconductive semiconductor switches (PCSSs) used in pulsed-power drivers, high-power microwave (HPM) sources, and high-voltage gate drivers for wide bandgap (WBG) power electronics.

Carbon-dopped Gallium nitride (GaN:C)↗
DOE OSTI2020

Optimal Power Hardware-in-the-Loop Interfacing: Applying Modern Control For Design and Verification of High-Accuracy Interfaces

Here, we develop a novel approach to designing power hardware-in-the-loop (PHIL) simulation interfaces that maximizes simulation bandwidth and accuracy by leveraging a modern control framework that explicitly considers objectives on accuracy and can automatically synthesize an optimal controller that meets these objectives while stabilizing the closed-loop system. The method developed improves upon common approaches to PHIL interface design that typically involve multiple design steps for manual compensation and stabilization design that can result in interfaces that are stable but have suboptimal bandwidth and accuracy. The approach developed is general and can be applied to most PHIL system configurations. The modeling framework allows for the inclusion of scaling factors and hardware-under-test current injection models that are common to practical PHIL simulations and have significant impacts on stability. We also present practical methods and metrics for verifying the absolute accuracy of PHIL simulation results without relying on relative comparisons to potentially inaccurate models or previous simulation results. We demonstrate the accuracy evaluation method and show the improved performance achievable when using the optimal PHIL interface design approach in an experimental case study involving a 100-kVA battery inverter.

42 ENGINEERING↗
DOE OSTI2025

FedCSpc: A Cross-Silo Federated Learning System With Error-Bounded Lossy Parameter Compression

Cross-Silo federated learning is widely used for scaling deep neural network (DNN) training over data silos from different locations worldwide while guaranteeing data privacy. Communication has been identified as the main bottleneck when training large-scale models due to large-volume model parameters and gradient transmission across public networks with limited bandwidth. Most previous works focus on gradient compression, while limited work tries to compress parameters that can not be ignored and extremely affect communication performance during the training. Here, to bridge this gap, we propose FedCSpc: an efficient cross-silo federated learning system with an XAI-driven adaptive parameter compression strategy for large-scale model training. Our work substantially differs from existing gradient compression techniques due to the distinct data features of gradient and parameter. The key contributions of this paper are fourfold. (1) Our designed FedCSpc proposes to compress the parameter during the training using the state-of-the-art error-bounded lossy compressor – SZ3. (2) We develop an adaptive compression error bound adjustment algorithm to guarantee the model accuracy effectively. (3) We exploit an efficient approach to utilize the idle CPU resources of clients to compress the parameters. (4) We perform a comprehensive evaluation with a wide range of models and benchmarks on a GPU cluster with 65 GPUs. Results show that FedCSpc can achieve the same model accuracy as FedAvg while reducing the data volume of parameters and gradients in communication by up to 7.39× and 288×, respectively. With 32 clients on a 4 Gb size model, FedCSpc significantly outperforms FedAvg in wall-clock time in the emulated WAN environment (at the bandwidth of 1 Gbps or lower without loss of generality).

SZ3↗
DOE OSTI2020

Flux Balancing Control of Ungapped Nanocrystalline Core-Based Transformer in Dual Active Bridge Converters

Transformer flux dc bias is a critical issue, impacting the reliable operation of dual active bridge (DAB) converters especially when ungapped high permeability nanocrystalline core is used. Steady state current dc bias can easily saturate ungapped nanocrystalline transformers, and it is even more dangerous in transient conditions. A dc bias model is proposed to analyze steady state dc bias in different load conditions. The magnetizing current detection is necessary for closed-loop control of dc bias; conductors' position is shown to impact sensor noise, and it is analyzed in detail. To deal with both steady state and transient dc bias, a unified flux balancing control (UFBC) is proposed introducing a predictive bias suppression (PBS) method with closed-loop flux balancing control (CFBC). With the proposed PBS, both primary/secondary current balance and flux balance can be achieved within one switching cycle using UFBC. Power characteristics and interaction between power control and flux balancing control of DAB converters are analyzed, and the CFBC needs to work in a low bandwidth due to sensor bandwidth limitation and interaction between power control and flux balancing control. Lastly, the UFBC is verified on a 300-kW cascaded DAB converter prototype.

42 ENGINEERING↗
DOE OSTI2024

Software-Defined Virtual Synchronous Condenser

Synchronous condensers (SCs) play important roles in integrating wind energy into relatively weak power grids. However, the design of SCs usually depends on specific application requirements and may not be adaptive enough to the frequently-changing grid conditions caused by the transition from conventional to renewable power generation. This paper devises a software-defined virtual synchronous condenser (SDViSC) method to address the challenges. Our contributions are fourfold: 1) design of a virtual synchronous condenser (ViSC) to enable full converter wind turbines to provide built-in SC functionalities; 2) engineering SDViSCs to transfer hardware-based ViSC controllers into software services, where a Tustin transformation-based software-defined control algorithm guarantees accurate tracking of fast dynamics under limited communication bandwidth; 3) a software-defined networking-enhanced SDViSC communication scheme to allow enhanced communication reliability and reduced communication bandwidth occupation; and 4) Prototype of SDViSC on our real-time, cyber-in-the-loop digital twin of large-wind-farm in an RTDS environment. Furthermore, extensive test results validate the excellent performance of SDViSC to support reliable and resilient operations of wind farms under various physical and cyber conditions.

17 WIND ENERGY↗
DOE OSTI2020

Design and Analysis of the Staggered Double Grating Slow Wave Circuit for 263 GHz Sheet Beam TWT

The complete design process of a high-frequency circuit for a 263 GHz staggered double grating, sheet beam traveling wave tube is presented in this article. Here, this device, for use in a pulsed electron paramagnetic resonance spectrometer instrument, requires >30 dB gain and a 20 GHz bandwidth centered at 263 GHz. In addition to the standard Pierce gain analysis and point by point particle in cell (PIC) simulation, a novel fast pulse response analysis technique was utilized to determine the accurate synchronization voltage and test the ``hot” feature of the high-frequency circuit. Since this new method can evaluate the entire bandwidth in a single simulation, it can significantly reduce the computational resources normally required for the conventional PIC analysis while also illustrating the potential instabilities near the band edge. Good agreement between the fast pulse response and PIC simulation results validate the accuracy of this novel method. According to the analysis results and given the manufacturing limits of nano/micro-computer numerical control (CNC) machining, an appropriate SWS, coupler, and sever designs were chosen to complement the simulated design. Finally, a prototype circuit was manufactured and cold tested to verify the design and inspect the machining tolerances.

42 ENGINEERING↗
DOE OSTI2022

Calibration, modeling, parameterization, and verification of the instrument transfer function of an interferometric microscope

Interferometric microscopes are used to measure surface roughness, from which the computed power spectral density function can be used to extract bandwidth-limited values of the various surface properties, such as root-mean-square (rms) height and slope errors. Measurements with a microscope equipped with different objectives that have an overlapping spatial frequency range usually give different rms results over the common frequency bandwidth. This is a result of different instrument transfer functions (ITFs) that attenuate spatial frequencies by different amounts over the overlapping range. We report on the use of binary pseudo-random array (BPRA) standards to characterize the ITF of an interferometric microscope with the various objectives. We use a simple model of a 1D binary Results show that the spectrum for an undersampled array is a cosine function, rather than a straight line, constant white noise spectrum. We have an analytical model of the ITF that includes the effects of an obscured aperture and defocus, in addition to the usual parameters of numerical aperture, wavelength, and sampling period. In addition, the model includes the effect of aliasing of spatial frequency components beyond the Nyquist back into the sub-Nyquist region. We compare the model PSD predictions to the measurements performed with different objectives. Departures of the measured PSDs from the model predictions indicate that there are higher-order ITF corrections yet to be identified and included in the model.

Takacs, PZ↗
DOE OSTI2022

Investigation of Microwave Transducers for Linearity Dependence and Applications in Quantum Networking

Quantum devices have the potential to revolutionize applications in computing, communications, and sensing; however, current state-of-art resources must operate at extremely low temperatures, making the routing of microwave control and readout signals challenging to scale. Interest in microwave photonic solutions to this problem has grown in recent years, in which control signals are delivered to the cold stage via optical fiber, where they are converted to electrical signals through photodetection. Overall link performance depends strongly on the characteristics of the photodiode, yet detailed measurements of many detector properties remain lacking at cold temperatures. In this work, we examine and compare the performance of a modified uni-traveling carrier photodiode (MUTC-PD) at both room (300 K) and liquid nitrogen (80 K) temperatures, focusing in particular on responsivity, bandwidth, and linearity. In line with previous work, we find a sharp reduction in responsivity at 1550 nm as temperature decreases, while RF bandwidth remains steady. Interestingly, our linearity tests reveal that the RF output saturates more quickly at 80 K, suggesting reduced linearity with lower temperature, the cause of which is still under investigation. Our results should help contribute to the understanding and future design of highly linear cryogenic quantum links.

Bolton, Summer↗
DOE OSTI2020

Stability Analysis of Inline ZFP Compression for Floating-Point Data in Iterative Methods

Currently, the dominating constraint in many high performance computing applications is data capacity and bandwidth, in both internode communications and even moreso in intranode data motion. A new approach to address this limitation is to make use of data compression in the form of a compressed data array. Storing data in a compressed data array and converting to standard IEEE-754 types as needed during a computation can reduce the pressure on bandwidth and storage. However, repeated conversions (lossy compression and decompression) introduce additional approximation errors, which need to be shown to not significantly affect the simulation results. Here, we extend recent work that analyzed the error of a single use of compression and decompression of the ZFP compressed data array representation to the case of time-stepping and iterative schemes, where an advancement operator is repeatedly applied in addition to the conversions. We show that the accumulated error for iterative methods involving fixed-point and time evolving iterations is bounded under standard constraints. An upper bound is established on the number of additional iterations required for the convergence of stationary fixed-point iterations. An additional analysis of traditional forward and backward error of stationary iterative methods using ZFP compressed arrays is also presented. The results of several 1D, 2D, and 3D test problems are provided to demonstrate the correctness of the theoretical bounds.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

PC-RPL: Joint Control of Routing Topology and Transmission Power in Real Low-Power and Lossy Networks

We present PC-RPL , a transmission power-controlled IPv6 routing protocol for low-power and lossy wireless networks that significantly improves the end-to-end packet delivery performance under heavy traffic compared to the standard RPL. We show through actual design, implementation, and experiments that a multihop wireless network can achieve better throughput and routing stability when transmission power and routing topology are “jointly and adaptively” controlled. Our experiments show that the predominant “fixed and uniform” transmission power strategy with “link quality and hop distance”–based routing topology construction (i.e., RPL) loses significant bandwidth due to hidden terminal and load imbalance problems. We design an adaptive and distributed control mechanism for transmission power and routing topology, named PC-RPL , on top of the standard RPL routing protocol for hidden terminal mitigation and load balancing. We implement PC-RPL on real embedded devices and evaluate its performance on a 49-node multihop testbed. PC-RPL reduces total end-to-end packet losses by approximately sevenfold without increasing hop distance compared to RPL with the highest transmission power, resulting in 17% improvement in aggregate bandwidth and 64% improvement for the worst-case node by successfully alleviating both hidden terminal and load imbalance problems.

Computer Science↗
DOE OSTI2020

Programming Strategies for Irregular Algorithms on the Emu Chick

The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

Hein, Eric↗
DOE OSTI2021

Mitigating Inter-Job Interference via Process-Level Quality-of-Service

Jobs on most high-performance computing (HPC) systems share the network with other concurrently executing jobs. Network sharing leads to contention that can severely degrade performance. Here we investigate the use of Quality of Service (QoS) mechanisms to reduce the negative impacts of network contention. QoS allows users to manage resource sharing between network flows and to provide bandwidth guarantees to specific flows. Our results show that careful use of QoS reduces the impact of network contention for specific jobs, resulting in up to a 40% performance improvement. In some cases, it completely eliminates the impact of contention. It achieves these improvements with limited negative impact to other jobs; any job that experiences performance loss typically degrades less than 5%, and often much less. Our approach can help ensure that HPC machines maintain high levels of throughput as per-node compute power continues to increase faster than network bandwidth.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Single-node Partitioned-Memory for Huge Graph Analytics: Cost and Performance Trade-offs

Nonvolatile memory NVDIMMs, available as Intel Optane, are less expensive than DRAM and bring large byte-addressable storage within reach to many applications. Evaluations on graph analytics have shown promising performance only when DRAM is used as a hardware cache (Memory mode). An open question is whether graph applications can exploit Optane and DRAM directly (AppDirect mode) and achieving better-than-DRAM average bandwidth and run times. We evaluate Optane as a volatile pool on two large-scale graph applications with very different computational patterns, Grappolo and Ripples. We show that AppDirect mode can deliver better-than-DRAM performance, by allocating data structures to Optane and DRAM according to their access characteristics, resulting in higher average memory bandwidth and lower average latency. Memory mode provides DRAM-competitive performance with capacity equal to persistent memory. We demonstrate occasional 4x improvement using the latest AppDirect option and frequently observe competitive performance between Optane AppDirect Memory modes and DRAM.

Ghosh, Sayan↗
DOE OSTI2022

Access Patterns and Performance Behaviors of Multi-layer Supercomputer I/O Subsystems under Production Load

Scientific computing workloads at HPC facilities have been shifting from traditional numerical simulations to AI/ML applications for training and inference while processing and producing ever-increasing amounts of scientific data. To address the growing need for increased storage capacity, lower access latency, and higher bandwidth, emerging technologies such as non-volatile memory are integrated into supercomputer I/O subsystems. With these emerging trends, we need a better understanding of the multilayer supercomputer I/O systems and ways to use these subsystems efficiently. In this work, we study the I/O access patterns and performance characteristics of two representative supercomputer I/O subsystems. Through an extensive analysis of year-long I/O logs on each system, we report new observations in I/O reads and writes, unbalanced use of storage system layers, and new trends in user behaviors at the HPC I/O middleware stack.

Bez, JL↗
DOE OSTI2023

Scalable Incremental Checkpointing using GPU-Accelerated De-Duplication

Writing large amounts of data concurrently to stable storage is a typical I/O pattern of many HPC workflows. This pattern introduces high I/O overheads and results in increased storage space utilization especially for workflows that need to capture the evolution of data structures with high frequency as checkpoints. In this context, many applications, such as graph pattern matching, perform sparse updates to large data structures between checkpoints. For these applications, incremental checkpointing techniques that save only the differences from one checkpoint to another can dramatically reduce the checkpoint sizes, I/O bottlenecks, and storage space utilization. However, such techniques are not without challenges: it is non-trivial to transparently determine what data has changed since a previous checkpoint and assemble the differences in a compact fashion that does not result in excessive metadata. State-of-art data reduction techniques (e.g., compression and de-duplication) have significant limitations when applied to modern HPC applications that leverage GPUs: slow at detecting the differences, generate a large amount of metadata to keep track of the differences, and ignore crucial spatiotemporal checkpoint data redundancy. This paper addresses these challenges by proposing a Merkle tree-based incremental checkpointing method to exploit GPUs' high memory bandwidth and massive parallelism. Experimental results at scale show a significant reduction of the I/O overhead and space utilization of checkpointing compared with state-of-the-art incremental checkpointing and compression techniques.

Tan, Nigel↗
DOE OSTI2024

Tailor : Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this article, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network’s skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware-efficient implementation with minimal to no accuracy loss. We introduceTailor, a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network’s skip connections to lower the hardware cost.Tailorimproves resource utilization by up to 34% for block random access memories (BRAMs), 13% for flip-flops (FFs), and 16% for look-up tables (LUTs) for on-chip, dataflow-style architectures.Tailorincreases performance by 30% and reduces memory bandwidth by 45% for a two-dimensional processing element array architecture.

Computer Science↗