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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A feasible path for the use of ferromagnetic josephson junctions in quantum circuits: The ferro-transmon

We discuss the capabilities of ferromagnetic (F) Josephson junctions (JJs) in a variety of layouts and configurations. The main goal is to demonstrate the potential of these hybrid JJs to disclose new physics and the possibility to integrate them in superconducting classical and quantum electronics for various applications. The feasible path towards the use of ferromagnetic Josephson junctions in quantum circuits starts from experiments demonstrating macroscopic quantum tunneling in NbN/GdN/NbN junctions with ferro-insulator barriers and with triplet components of the supercurrent, supported by a self-consistent electrodynamic characterization as a function of the barrier thickness. This has inspired further studies on tunnel ferromagnetic junctions with a different layout and promoted the first generation of ferromagnetic Al-based JJs, specifically Al/AlO x /Al/Py/Al. This layout takes advantage of the capability to integrate the ferromagnetic layer in the junction without affecting the quality of the superconducting electrodes and of the tunnel barrier. The high quality of the devices paves the way for the possible implementation of Al tunnel-ferromagnetic JJs in superconducting quantum circuits. These achievements have promoted the notion of a novel type of qubit incorporating ferromagnetic JJs. This qubit is based on a transmon design featuring a tunnel JJ in parallel with a ferromagnetic JJ inside a SQUID loop capacitively coupled to a superconducting readout resonator. In conclusion, the effect of an external RF field on the magnetic switching processes of ferromagnetic JJs has been also investigated.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2006

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Field Programmable Gate Arrays↗
DOE OSTI2022

Module-Fluidics: Building Blocks for Spatio-Temporal Microenvironment Control

Generating the desired solute concentration signal in micro-environments is vital to many applications ranging from micromixing to analyzing cellular response to a dynamic microenvironment. We propose a new modular design to generate targeted temporally varying concentration signals in microfluidic systems while minimizing perturbations to the flow field. The modularized design, here referred to as module-fluidics, similar in principle to interlocking toy bricks, is constructed from a combination of two building blocks and allows one to achieve versatility and flexibility in dynamically controlling input concentration. The building blocks are an oscillator and an integrator, and their combination enables the creation of controlled and complex concentration signals, with different user-defined time-scales. We show two basic connection patterns, in-series and in-parallel, to test the generation, integration, sampling and superposition of temporally-varying signals. All such signals can be fully characterized by analytic functions, in analogy with electric circuits, and allow one to perform design and optimization before fabrication. Such modularization offers a versatile and promising platform that allows one to create highly customizable time-dependent concentration inputs which can be targeted to the specific application of interest.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

Circuit Modeling, Simulation, and Experimental Validation of a 100-kW Polyphase Wireless Power Transfer System for EV Applications

Polyphase wireless power transfer (WPT) systems can achieve much higher surface power densities (kW/m2) and specific power levels (kW/kg) compared to the conventional circular single phase WPT systems. Therefore, polyphase WPT systems can reduce the size, weight, volume, and cost of the WPT systems and can simplify the electric vehicle integration with less demand for space. This study presents the high-performance and compact 100-kW WPT development using polyphase electromagnetic coupling coils with rotating magnetic fields.

Onar, Omer [ORNL] (ORCID:0000000292028857)↗
NASA NTRS1996

Compiled Data On Single-Event Effects Caused By Heavy Ions

Report presents test data on susceptibility of new set of digital integrated circuits and other semiconductor products to single-event effects (soft errors and latchups) caused by heavy ions incident at high energies. Data used to develop generalizations for protecting electronic equipment from single-event effects. In some cases, tested parts selected as candidates for use in specific applications.

Nichols, Donald K.↗
NASA NTRS2003

Microbatteries for Combinatorial Studies of Conventional Lithium-Ion Batteries

Integrated arrays of microscopic solid-state batteries have been demonstrated in a continuing effort to develop microscopic sources of power and of voltage reference circuits to be incorporated into low-power integrated circuits. Perhaps even more importantly, arrays of microscopic batteries can be fabricated and tested in combinatorial experiments directed toward optimization and discovery of battery materials. The value of the combinatorial approach to optimization and discovery has been proven in the optoelectronic, pharmaceutical, and bioengineering industries. Depending on the specific application, the combinatorial approach can involve the investigation of hundreds or even thousands of different combinations; hence, it is time-consuming and expensive to attempt to implement the combinatorial approach by building and testing full-size, discrete cells and batteries. The conception of microbattery arrays makes it practical to bring the advantages of the combinatorial approach to the development of batteries.

West, William↗
DOE OSTI2020

Solution-processable integrated CMOS circuits based on colloidal CuInSe2 quantum dots

Abstract The emerging technology of colloidal quantum dot electronics provides an opportunity for combining the advantages of well-understood inorganic semiconductors with the chemical processability of molecular systems. So far, most research on quantum dot electronic devices has focused on materials based on Pb- and Cd chalcogenides. In addition to environmental concerns associated with the presence of toxic metals, these quantum dots are not well suited for applications in CMOS circuits due to difficulties in integrating complementary n - and p -channel transistors in a common quantum dot active layer. Here, we demonstrate that by using heavy-metal-free CuInSe 2 quantum dots, we can address the problem of toxicity and simultaneously achieve straightforward integration of complimentary devices to prepare functional CMOS circuits. Specifically, utilizing the same spin-coated layer of CuInSe 2 quantum dots, we realize both p - and n -channel transistors and demonstrate well-behaved integrated logic circuits with low switching voltages compatible with standard CMOS electronics.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1996

Micromachined Ion Accelerators

Proposed ion accelerators made by micromachining techniques. Advantages include small size and weight, modularity, and compatibility with integrated circuits. Used as sources of ion beams for industrial processes. Ion accelerator of this type combined with integrated electronic control and power circuitry, plus similarly miniaturized valves and other mechanisms for regulating flow of gas used to generate ions - all micromachined on single chip. Provides flexibility for tailoring characteristics of ion sources for specific applications; for example, construct array of many such devices to obtain large ion source or position multiple devices to obtain desired ion-beam pattern in processing chamber.

Brophy, John↗
DOE OSTI2023

Integration of Ultrawide Bandgap Photoconducting Semiconductor Switches into High-Voltage, High-Current Pulser Systems

In this feasibility study we will evaluate the viability of integrating ultrawide bandgap (UWBG) photoconducting semiconductor switches (PCSS) in high-voltage pulser systems capable of driving low-impedance dynamic loads critical for next-generation accelerator and RF-source applications. The project consisted of developing modelling tools that would inform design of UWBG PCSS packages that could be mounted onto conventional circuit boards. Specifically, we are interested in evaluating the following through simulation software: (1) resistance to electrical breakdown (2) proximity effects due to high-frequency skin effect (3) transient behavior from switching (4) effective transmission of RF signals (5) thermal dynamics of the switch under operation (6) sensitivity to inhomogeneities in optical excitation of the material (7) cross-talk effects from parallel switching structures, and (8) susceptibility of system to damaged components. The project resulted in the development of a special-purpose circuit code that implements photoconductivity physics. This code was used to evaluate objectives 1-6 above, identifying a critical requirement associated with the need for fine control of dopant concentrations in the UWBG material to reach an optimal solution for voltage standoff and laser light responsivity requirements. In addition, we identified that the temperature dependence of the electrical conductivity of this material was typically not well-measured and developed a platform for measuring both the “dark” and “illuminated” conductivity on real physical switches in the lab to better inform our models.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1993

Testing self-timed circuits using scan paths

Testing is an essential part of any digital system design and one that can be made much easier if testing is considered during the design process rather than after the system is complete. There are a number of techniques for integrating testability into system design, but many of these traditional testing methods used for synchronous circuits are not directly applicable to non-clocked asynchronous circuits. As a result, many asynchronous circuits do not employ design for testability techniques. A method of using the familiar model of scan paths modified to test self-timed systems are presented. Specifically, circuits designed using a library of self-timed modules to assemble systems with two-phase transition control and bundled data paths are considered. The method involves modifying these self-timed modules such that circuits designed from them have a built-in scan path.

Khoche, Ajay↗
DOE OSTI2020

Sensors with Intelligent Measurement Platform for Monitoring and Control in Distribution Circuits

This paper presents a medium-voltage intelligent measurement platform that provides post-processing of raw measurements received from commercially-available voltage/current sensors to enhance accuracy and bandwidth of the monitoring system. Furthermore, this platform integrates into a Data Distribution Service (DDS) messaging bus for distributed control and interoperability. The authors present the design, specifications, and major components included in the platform, and argue for applications and use cases that most benefit from this new approach. A laboratory testbed has been created to demonstrate the functionality, for which test results are presented for selected test cases.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2016

Command and Data Handling Branch Internship

Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments (TI)' MSP430 16-bit ultra-low-power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display (LCD) touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320 by 240 RGB resistive color screen including an optional carrier board. The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA (Field Programmable Gate Array) development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At the moment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process. Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments’ MSP430 16 bit ultra-low power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320x240 RGB resistive color screen including an optional carrier board.The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At themoment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process.Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate school for a master's or doctorate degree in electrical or computer engineering.

Billings, Rachel Mae↗
DOE OSTI2024

Detecting defects that reduce breakdown voltage using machine learning and optical profilometry

Abstract Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (V bk ). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary.

42 ENGINEERING↗
NASA NTRS2009

Large-Aperture Membrane Active Phased-Array Antennas

Large-aperture phased-array microwave antennas supported by membranes are being developed for use in spaceborne interferometric synthetic aperture radar systems. There may also be terrestrial uses for such antennas supported on stationary membranes, large balloons, and blimps. These antennas are expected to have areal mass densities of about 2 kg/sq m, satisfying a need for lightweight alternatives to conventional rigid phased-array antennas, which have typical areal mass densities between 8 and 15 kg/sq m. The differences in areal mass densities translate to substantial differences in total mass in contemplated applications involving aperture areas as large as 400 sq m. A membrane phased-array antenna includes patch antenna elements in a repeating pattern. All previously reported membrane antennas were passive antennas; this is the first active membrane antenna that includes transmitting/receiving (T/R) electronic circuits as integral parts. Other integral parts of the antenna include a network of radio-frequency (RF) feed lines (more specifically, a corporate feed network) and of bias and control lines, all in the form of flexible copper strip conductors on flexible polymeric membranes. Each unit cell of a prototype antenna (see Figure 1) contains a patch antenna element and a compact T/R module that is compatible with flexible membrane circuitry. There are two membrane layers separated by a 12.7-mm air gap. Each membrane layer is made from a commercially available flexible circuit material that, as supplied, comprises a 127-micron-thick polyimide dielectric layer clad on both sides with 17.5-micron-thick copper layers. The copper layers are patterned into RF, bias, and control conductors. The T/R module is located on the back side of the ground plane and is RF-coupled to the patch element via a slot. The T/R module is a hybrid multilayer module assembled and packaged independently and attached to the membrane array. At the time of reporting the information for this article, an 8 16 passive array (not including T/R modules) and a 2 4 active array (including T/R modules) had been demonstrated, and it was planned to fabricate and test larger arrays.

Karasik, Boris↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS1987

Advanced Components for Spaceborne Infrared Astronomy

Basic improvements in the technology of low noise read-out systems for low background detectors were demonstrated. Using discrete JFET integrating amplifiers at their optimum temperature of 55 K, read noise less than 7.5 electrons in 128 seconds of integration was obtained. Two models of single channel integrators are now available, the JF-77 for use between 50 and 80 K and the JF-4 for lower temperatures. A 1 x 15 linear array of complete integrators on a single integrated circuit was developed and will be made available in the near future. The successful operation of a superconducting stepper motor was demonstrated. The motor shows a three fold increase in torque over conventional motors operating at room temperature. The success of the motor stems from the use of superconducting coils in conjunction with developments in bearings for cryogenic use, rare-earth rotors, and motor cooling techniques. The current state of development will allow the rapid development of motors optimized for specific applications. An electronic switch capable of resetting cooled JFET integrating amplifiers was developed. The JFET integrating amplifiers that use this switch have demonstrated read noise of less than 10 electrons. The JFET reset device exhibits an extremely high open impedance and low leakage current. Capacitance is sufficiently low so as not to impair amplifier sensitivity. The effects of transient switching charges are minimized by a compensation technique and variable transient current problems inherent to devices of this type are overcome by external circuity.

Davidson, Arnold W.↗
DOE OSTI2024

Development of CMOS Sensors for HEP with a US-based foundry

We will present a program to establish the first development and manufacturing of HEP-specific sensors monolithically integrated into a standard CMOS process using a US-based foundry. In collaboration with several US universities the project aims to develop Monolithic Active Pixel Sensors (MAPS) designs implemented in the 90 nm technology node, including simple test structures and multi-pixel arrays, and monolithic CMOS sensors with readout integrated circuits, perform detailed characterization of the detector prototypes and quantify their performance for HEP applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗