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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

RAFT: Reconfigurable Array of High-Efficiency Ducted Turbines for Hydrokinetic Energy Harvesting

Diversifying the energy harvesting portfolio is crucial to achieving the ambitious goal of transitioning to clean energy by 2030. Marine hydrokinetic energy has garnered renewed interest due to its high harvesting potential in the U.S., and the resource's reliability and predictability—remaining relatively constant on a daily basis and available 24/7. However, there are currently few commercial devices capable of harnessing the energy from flowing water. This project aims to bridge that gap by designing and evaluating a novel hydrokinetic turbine concept that can efficiently harvest energy from both rivers and tidal streams. The RAFT (Reconfigurable Array of High-Efficiency Ducted Turbines) concept introduces a duct surrounding the turbine rotor and creates an array of small 5-kW units. The duct serves two primary purposes: (1) it enhances hydrodynamic efficiency by accelerating flow to the rotor, and (2) it functions as a structural component, facilitating the formation of modular arrays that lower costs. This project focuses on demonstrating this concept and validating these benefits through simulations and scaled prototype testing. The project team includes 8 faculty members and over 20 students from 3 universities, organized into three core areas: hydrodynamics, electrical systems, and structural analysis, with additional teams dedicated to system integration, environmental assessment and risk management, and tech-to-market strategy. The team successfully demonstrated the increased hydrodynamic efficiency of a ducted turbine compared to an unducted version using high-fidelity simulations and prototype tests. Moreover, design optimization efforts led to surpassing the SHARKS program's goal of 60% reduction of the levelized cost of energy with a significant margin.

13 HYDRO ENERGY↗
DOE OSTI2025

Reconfigurable neuromorphic components and algorithms for next-generation artificial intelligence

Digital transistor-based general-purpose hardware (e.g., central processing units) is the dominant solution to support both traditional computing (logic, arithmetic, etc.) as well as modern artificial intelligence. State-of-the-art research has shown feasibility of post-digital physics-based neuromorphic hardware, which is hypothesized to support artificial intelligence algorithms with orders-of-magnitude improved time/energy efficiencies. But such research has not been widely deployed mainly because of such novel hardware’s extreme application-specificity, and the dominance of low-cost general-purpose (but inefficient) digital hardware. To make use of the novel algorithms and the superlative performance of physics-based hardware, we need to identify scientific principles that can enable generality in physics-based hardware. This work resulted in two important broad outcomes – first, we demonstrate fully reconfigurable neuromorphic components, and second, we demonstrate a viable artificial intelligence learning algorithm that can exploit the functioning of neuromorphic hardware. We demonstrate up to five orders of magnitude improvement in energy efficiency compared to the best general-purpose digital hardware.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1971

Reconfigurable G and C computer study for space station use. Volume 7, appendix 5 - D-200 computer family. Appendix 6 - System error analysis. Appendix 7 - Reliability derivation for candidate computers. Appendix 8 - Power converter design data. Appendix 9 - Data transmission medium design Final report, 29 Dec. 1969 - 31 Jan. 1971

D-200 computer family, system error analysis, reliability derivation, and power converter design for reconfigurable guidance and control computer - Vol. 7

Source record↗
NASA NTRS1976

Reconfigurable redundancy management for aircraft flight control

A highly fault tolerant digital computer system has been configured based on extensive experience with flight proven, redundant digital flight control systems. The feasibility of minimizing hardware complexity is shown while maintaining high levels of fault tolerance. The emerging hardware design combines reconfiguration concepts with conventional hardware redundancy techniques and special operational software to provide dual fail operate performance with a basic triplex system. The design provides high reliability and flight safety, enhances maintainability, and reduces life cycle cost while offering improved performance for future aircraft.

Bosch, J. A.↗
NASA NTRS1979

On reliable control system designs with and without feedback reconfigurations

This paper contains an overview of a theoretical framework for the design of reliable multivariable control systems, with special emphasis on actuator failures and necessary actuator redundancy levels. Using a linear model of the system, with Markovian failure probabilities and quadratic performance index, an optimal stochastic control problem is posed and solved. The solution requires the iteration of a set of highly coupled Riccati-like matrix difference equations; if these converge one has a reliable design; if they diverge, the design is unreliable, and the system design cannot be stabilized. In addition, it is shown that the existence of a stabilizing constant feedback gain and the reliability of its implementation is equivalent to the convergence properties of a set of coupled Riccati-like matrix difference equations. In summary, these results can be used for offline studies relating the open loop dynamics, required performance, actuator mean time to failure, and functional or identical actuator redundancy, with and without feedback gain reconfiguration strategies.

Birdwell, J. D.↗
NASA NTRS1979

Self-reconfiguring solar cell system

A self-reconfiguring solar cell array is disclosed wherein some of the cells are switched so that they can be either in series or in shunt within the array. This feature of series or parallel switching of cells allows the array to match the load to achieve maximum power transfer. Automatic control is used to determine the conditions for maximum power operation and to switch the array into the appropriate configuration necessary to transfer maximum power to the load.

Gruber, R. P.↗
NASA NTRS1980

A polymorphic reconfigurable emulator for parallel simulation

Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described.

Parrish, E. A., Jr.↗
NASA NTRS1982

Electrically reconfigurable logic array

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Agarwal, R. K.↗
NASA NTRS1984

Reconfigurable multivariable control law for commercial airplane using a direct digital output feedback design

The ability of a pilot to reconfigure the control surfaces on an airplane after a failure, allowing the airplane to recover to a safe condition for landing, becomes more difficult with increasing airplane complexity. Techniques are needed to stabilize and control the airplane immediately after a failure, allowing the pilot time to make longer range decisions. This paper shows a design of a discrete multivariable control law using four controls for the longitudinal channel of a B-737. Single control element failures are allowed in three of the four controls. The four controls design and failure cases are analyzed by means of a digital airplane simulation, with regard to tracking capability and ability to overcome severe windshear and turbulence during the aproach and landing phase of flight.

Ostroff, A. J.↗
NASA NTRS1983

Fault detection, isolation and reconfiguration in FTMP Methods and experimental results

The Fault-Tolerant Multiprocessor (FTMP) is a highly reliable computer designed to meet a goal of 10 to the -10th failures per hour and built with the objective of flying an active-control transport aircraft. Fault detection, identification, and recovery software is described, and experimental results obtained by injecting faults in the pin level in the FTMP are presented. Over 21,000 faults were injected in the CPU, memory, bus interface circuits, and error detection, masking, and error reporting circuits of one LRU of the multiprocessor. Detection, isolation, and reconfiguration times were recorded for each fault, and the results were found to agree well with earlier assumptions made in reliability modeling.

Lala, J. H.↗
NASA NTRS1987

Failure detection and identification for a reconfigurable flight control system

Failure detection and identification logic for a fault-tolerant longitudinal control system were investigated. Aircraft dynamics were based upon the cruise condition for a hypothetical transonic business jet transport configuration. The fault-tolerant control system consists of conventional control and estimation plus a new outer loop containing failure detection, identification, and reconfiguration (FDIR) logic. It is assumed that the additional logic has access to all measurements, as well as to the outputs of the control and estimation logic. The pilot may also command the FDIR logic to perform special tests.

Dallery, Francois↗
NASA NTRS1987

Reconfigurable tree architectures using subtree oriented fault tolerance

An approach to the design of reconfigurable tree architecture is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is 0(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.

Lowrie, Matthew B.↗