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Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.
A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.
The invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures at least some of which are anchored laterally to the remainder of the substrate. Electrical isolation at points where mechanical structures are attached to the substrate is provided by filled isolation trenches. Filled trenches may also be used to electrically isolate structure elements from each other at points where mechanical attachment of structure elements is desired. The performance of microelectromechanical devices is improved by 1) having a high-aspect-ratio between vertical and lateral dimensions of the mechanical elements, 2) integrating electronics on the same substrate as the mechanical elements, 3) good electrical isolation among mechanical elements and circuits except where electrical interconnection is desired.
The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.
A process for growing multiwalled carbon nanotubes anchored at specified locations and aligned along specified directions has been invented. Typically, one would grow a number of the nanotubes oriented perpendicularly to a silicon integrated-circuit (IC) substrate, starting from (and anchored on) patterned catalytic spots on the substrate. Such arrays of perpendicular carbon nanotubes could be used as electrical interconnections between levels of multilevel ICs. The process (see Figure 1) begins with the formation of a layer, a few hundred nanometers thick, of a compatible electrically insulating material (e.g., SiO(x) or Si(y)N(z) on the silicon substrate. A patterned film of a suitable electrical conductor (Al, Mo, Cr, Ti, Ta, Pt, Ir, or doped Si), having a thickness between 1 nm and 2 m, is deposited on the insulating layer to form the IC conductor pattern. Next, a catalytic material (usually, Ni, Fe, or Co) is deposited to a thickness between 1 and 30 nm on the spots from which it is desired to grow carbon nanotubes. The carbon nanotubes are grown by plasma-enhanced chemical vapor deposition (PECVD). Unlike the matted and tangled carbon nanotubes grown by thermal CVD, the carbon nanotubes grown by PECVD are perpendicular and freestanding because an electric field perpendicular to the substrate is used in PECVD. Next, the free space between the carbon nanotubes is filled with SiO2 by means of CVD from tetraethylorthosilicate (TEOS), thereby forming an array of carbon nanotubes embedded in SiO2. Chemical mechanical polishing (CMP) is then performed to remove excess SiO2 and form a flat-top surface in which the outer ends of the carbon nanotubes are exposed. Optionally, depending on the application, metal lines to connect selected ends of carbon nanotubes may be deposited on the top surface. The top part of Figure 2 is a scanning electron micrograph (SEM) of carbon nanotubes grown, as described above, on catalytic spots of about 100 nm diameter patterned by electron-beam lithography. These and other nanotubes were found to have lengths ranging from 2 to 10 m and diameters ranging from 30 to 200 nm, the exact values of length depending on growth times and conditions and the exact values of diameter depending on the diameters and thicknesses of the catalyst spots. The bottom part of Figure 2 is an SEM of an embedded array of carbon nanotubes after CMP.
Objectives of NEXUS (NEXt bUS) (1) A research task funded by JPL R&TD program (2) Develop a common highly-capable next generation avionics interconnect with the following features: (a) Transparently compatible with wired, fiber-optic, and RF physical layers (b) A clear and feasible path-to-flight to ensure infusion into future NASA/JPL missions
A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.
The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.
The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.
A lens for interconnecting a metallic waveguide with a dielectric waveguide is provided. The lens may be coupled a metallic waveguide and a dielectric waveguide, and minimize a signal loss between the metallic waveguide and the dielectric waveguide.
A wide range of challenges must be overcome to conduct Urban Air Mobility (UAM)operations at scale with electric vertical take-off and landing aircraft as envisioned. This paper documents an analysis of one potential infrastructure challenge for UAM: available electrical grid power capacity. The success of UAM depends on the availability of electricity, which will be increasingly impacted by the proliferation of ground electric vehicles(EVs) over time. Under the best-case assumption that electricity can be transmitted and distributed as needed within each interconnection (i.e., electrical grid), it is estimated that the maximum number of UAM aircraft that can charge simultaneously in the continental United States will decrease by 20% from about 595 thousand in the year 2021 to about 475 thousand in the year 2050due to the projected increase in ground EVs.
A wide range of challenges must be overcome to conduct Urban Air Mobility (UAM)operations at scale with electric vertical take-off and landing aircraft as envisioned. This paper documents an analysis of one potential infrastructure challenge for UAM: available electrical grid power capacity. The success of UAM depends on the availability of electricity, which will be increasingly impacted by the proliferation of ground electric vehicles(EVs) over time. Under the best-case assumption that electricity can be transmitted and distributed as needed within each interconnection (i.e., electrical grid), it is estimated that the maximum number of UAM aircraft that can charge simultaneously in the continental United States will decrease by 20% from about 595 thousand in the year 2021 to about 475 thousand in the year 2050due to the projected increase in ground EVs.
NASA’s Artemis Program outlines the need for a habitat capable of sustaining human life as well as mining and producing raw materials on the lunar surface. This mission is viewed as a means towards deeper space exploration, with plans for reaching Mars and beyond. Human presence on the moon is not possible without the ability to generate and distribute energy, namely electricity, through a network of energy sources, loads, and power converters called a microgrid. Multiple microgrids can be deployed on the moon based on location and need. Separate microgrids will require interconnection to increase resiliency and reliability given the mission’s high criticality. A method for adaptive control over power converters connecting two dc microgrids is proposed. A simulation is modeled after the lunar power system with two approaches to power converter droop control, allowing for a more flexible and adaptive microgrid architecture. Further experiments are conducted using the control methods in a power hardware-in-the-loop test environment to study the performance of hardware converter control used in this application.
Key Considerations: - Long-term coordination and collaboration with utilities and ISOs may provide mutual benefits and support flexible interconnectivity. - Onsite storage and energy production can reduce load fluctuations and support grid resilience in the future. - Geography and resource availability can impact energy demand and grid flexibility.
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This report is part of the ongoing Solar Time-Based Residential Analytics and Cycle Time Estimator (SolarTRACE) project, led by the National Renewable Energy Laboratory (NREL). The SolarTRACE project utilizes time-stamped project-level data provided by installer-partners to assess nationwide and AHJ- and utility-level PI&I and other solar PV adoption timelines since 2017. Our dataset now covers 22% of residential solar and 33% of residential storage installs in the U.S. since 2017. This report provides an update to our previous 2022 report (Cruce et al., 2022b) and includes: updated 2017 2023 project timelines for residential rooftop solar PV up to 20kW; updated tracking of permitting process changes at nearly 4,000 AHJs nationwide; and first-ever reporting of timelines for residential PV+storage projects up to 20kW.
Integrated circuit packaging and their testing is well advanced because of the maturity of the IC industry, their wide applications, and availability of industrial infrastructure.