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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14

Object and Facial Recognition in Augmented and Virtual Reality: Investigation into Software, Hardware and Potential Uses

As augmented and virtual reality grows in popularity, and more researchers focus on its development, other fields of technology have grown in the hopes of integrating with the up-and-coming hardware currently on the market. Namely, there has been a focus on how to make an intuitive, hands-free human-computer interaction (HCI) utilizing AR and VR that allows users to control their technology with little to no physical interaction with hardware. Computer vision, which is utilized in devices such as the Microsoft Kinect, webcams and other similar hardware has shown potential in assisting with the development of a HCI system that requires next to no human interaction with computing hardware and software. Object and facial recognition are two subsets of computer vision, both of which can be applied to HCI systems in the fields of medicine, security, industrial development and other similar areas.

object recognition↗

An Overview of NASA-STD-1008: Classifications and Requirements for Testing Systems and Hardware to be Exposed to Dust in Planetary Environments

As we return to the Moon with Artemis, hardware will inevitably be exposed to lunar dust. Encountering the surface of a dusty planetary body brings significant hazards to the hardware. A team of subject matter experts across NASA were brought together to create a standard for addressing the best means of performing ground testing of hardware and systems to guard against the expected negative effects that dust may bring. This effort resulted in NASA-STD-1008: Classifications and Requirements for Testing Systems and Hardware to be Exposed to Dust in Planetary Environments. The NASA Technical Standard went through an Agency wide review and was approved for public release in September 2021.

lunar dust↗

Testing Mars 2020 Flight Software and Hardware in the Surface System Development Environment

The Mars 2020 (M2020) Perseverance Rover is NASA's most advanced planetary rover mission to date. It includes a novel Sample Caching Subsystem (SCS) which will collect rock cores for possible future return to Earth, as well as an improved mobility system with enhanced autonomous navigation which will enable it to traverse faster and farther than prior rovers. The development of both systems required extensive flight software and flight hardware testing. To support this testing, we developed the Surface System Development Environment (SSDEV) and used it for a wide variety of testing. SSDEV is a bundled subset of M2020 Flight Software which runs on commercially available Linux computers and can be combined with multiple backend options for simulation and hardware control. The SSDEV architecture enabled our teams to perform much more testing of flight software and flight hardware than would have otherwise been possible. As a secondary benefit, the SSDEV-based test campaigns also helped our teams enter the operations phase of the mission with greater readiness of operations products and tools. In this paper, we summarize the motivation for SSDEV, provide an overview of the SSDEV architecture, list several examples of how SSDEV was used, and summarize lessons learned. SSDEV is not a substitute for integrated testing with flight-like avionics, but it enabled substantially more testing than would have otherwise been possible and also provided some unique benefits. We recommend architectures like SSDEV to future projects that need to perform extensive hardware and software testing using a limited set of flight-like avionics.

Wai, Dennis↗

Hardware device to physical structure binding and authentication

Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

97 MATHEMATICS AND COMPUTING↗

Hardware device binding and mutual authentication

Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

97 MATHEMATICS AND COMPUTING↗

Constructing Hardware in a Scale Embedded Language

Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

Bachan, John↗

Processing unit performance projection using dynamic hardware behaviors

Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.

97 MATHEMATICS AND COMPUTING↗

Parallel Monte Carlo Methods for Heterogeneous Hardware Computer Systems Using GPUs and Coprocessors: Recent Development of ARCHER Code - Paper 54

Traditional methods of accelerating Monte Carlo (MC) calculations typically use CPUs as the computing unit. The parallelism is based upon multithreading on a multi-core processor, and message passing interface (MPI) across many processors and nodes. In recent years, the hardware accelerators have been introduced by the high performance computing industry as an alternative approach to achieve massive parallelism. Hardware accelerators have the advantage of high Floating-point Operations Per Second (FLOPS) and high energy efficiency. Examples include graphics processing units (GPUs) and coprocessors. Compute-intensive programs can be off-loaded to them to be concurrently executed by hundreds or thousands of active threads. Existing production MC codes, however, cannot be directly compiled or executed on the new platforms. It is therefore necessary to rewrite or redevelop the code using the hardware accelerator specific programming models and APIs. Several studies have been conducted on using GPUs to accelerate MC calculations in reactor analysis and medical physics. In this paper, we present the recent progress at Rensselaer Polytechnic Institute (RPI) in developing a new parallel MC code called ARCHER (Accelerated Radiation-transport Computations in Heterogeneous Environments) for coupled photon-electron transport simulations. The code is designed as a test bed to evaluate the efficacy of heterogeneous computing systems for low-cost MC-based radiation dosimetric calculations. The code has three variants corresponding to three parallel hardware platforms: ARCHER-CPU (multi-core CPU), ARCHER-GPU (Nvidia GPU) and ARCHER-COP (Intel Xeon Phi coprocessor). The code has been used for several applications, including CT imaging dosimetry, radiotherapy dosimetry and radiation shielding design. (authors)

61 RADIATION PROTECTION AND DOSIMETRY↗

Porting the Nonlinear Optimization Library HiOp to Accelerator-Based Hardware Architectures

While interior point method has been the centerpiece of nonlinear programming tools used in science and engineering, its reliance on linear solvers that can tackle sparse symmetric indefinite and highly ill-conditioned problems made it difficult to implement it effectively on hardware accelerators. HiOp optimization package attempts to provide an implementation of the interior point method suitable for hardware accelerators by compressing the original sparse problem to produce an underlying linear problem that is dense and of manageable size. Implementations of dense linear solvers are more mature and utilize hardware accelerators better than their sparse counterparts. There is a number of important domain problems, such as optimal power flow analysis for power grids, where the sparse problem can be effectively compressed and deploying dense linear solver within the interior point method can improve performance. Here we describe a portable implementation of HiOp optimization engine, which uses a linear solver from Magma library and runs entirely on hardware accelerators. To compress the problem, HiOp uses customized mixed dense-sparse linear algebra. All HiOp kernels are implemented using Umpire and RAJA portability libraries. We describe details of the implementation and discuss trade-offs between performance, portability and development cost.

97 MATHEMATICS AND COMPUTING↗

Performance Evaluation of a Single-Phase Grid-Forming Inverter Through Hardware Experiments: Preprint

Existing state-of-the-art of single-phase grid-forming (GFM) inverter are primarily focused on electromagnetic transient simulation, and there are very few works performing hardware test, and there is no clear understanding how the single-phase GFM inverter should behave from a hardware perspective. Therefore, this paper addresses the gap by performing hardware experiment to evaluate the performance of a single-phase GFM hardware inverter. We enrich the existing GFM testing protocols by investigating transient performance of GFM inverters under different grid dynamic events, and quantifiable performance metrics are made to have a common understanding of expected performance of single-phase GFM inverters. A commercial single-phase GFM inverter is used to verify the test protocols and understand the inverter's performance and functionalities.

dynamic events↗

Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware

Adiabatic logic is one of the circuit design techniques for designing energy-efficient hardware. In recent years, it has also been proved that this technique is suitable for designing secure hardware. In the existing literature, a Secured Quasi-Adiabatic Logic Family (SQAL) has recently been proposed in designing Differential Power Analysis (DPA)-resistant and energy-efficient hardware. SQAL shows improvement over all other existing DPA-resistant adiabatic logic in terms of energy dissipation and area-overhead. However, the drawback is, SQAL suffers from non-adiabatic energy loss during the evaluation of the outputs. To minimize the non-adiabatic loss, we propose in this paper a novel Symmetric Pass Gate Adiabatic Logic (SPGAL). SPICE simulations show that the bit-parallel cellular multiplier over GF(2 4 ) that we implemented using SPGAL saves up to 81% of energy as compared to SQAL at 12.5 MHz. Calculated values of Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) show that the proposed logic gates based on SPGAL consume uniform energy for every cycle of operation irrespective of their input transition. Finally, the uniform energy rate and low power operation shows that the proposed SPGAL is energy-efficient in nature and would be resistant to DPA attack at the circuit level.

97 MATHEMATICS AND COMPUTING↗

Hardware-in-the-Loop Evaluation of an Advanced Distributed Energy Resource Management Algorithm

This paper presents the laboratory performance evaluation of voltage regulation under a new distributed energy resource management system (DERMS) algorithm via an advanced hardware-in-tbe-loop (HIL) platform. The HIL platform provides realistic testing in a laboratory environment, including the accurate modeling of a full-scale real-world distribution system from a utility partner, the DERMS software controller, and power hardware photovoltaic (PV) inverters. The new DERMS algorithm is developed based on online multiobjective optimization (OMOO) algorithms that perform fast dispatch of distributed solar PV simulated in a real-time digital simulator and real physical hardware devices. Experimental tests confirm the correct functioning of the HIL platform for evaluating controller algorithms and satisfactory voltage regulation performance of the developed OMOO algorithms.

41 EE - Solar Energy Technologies Office (EE-4S)↗

Modeling and Compensation Design for a Power Hardware-in-the-Loop Simulation of an AC Distribution System

Power hardware-in-the-loop (PHIL) simulation, where actual hardware under text is coupled with a real-time digital model in closed loop, is a powerful tool for analyzing new methods of control for emerging distributed power systems. However, without careful design and compensation of the interface between the simulated and actual systems, PHIL simulations may exhibit instability and modeling inaccuracies. This paper addresses issues that arise in the PHIL simulation of a hardware battery inverter interfaced with a simulated distribution feeder. Both the stability and accuracy issues are modeled and characterized, and a methodology for design of PHIL interface compensation to ensure stability and accuracy is presented. The stability and accuracy of the resulting compensated PHIL simulation is then shown by experiment.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Hardware-in-the-Loop Simulation for the Proposed Slider-Crank Wave Energy Conversion Device

In this work, a novel model of a wave energy converter that utilizes a slider crank power take-off system (PTOS) is simulated in a hardware-in-the-loop framework. The simulated parts in this framework include a buoy, slider crank linkage, and a gearbox. The slider crank linkage acting as the linear to rotary converter is represented by a DC motor coupled with a physical generator. With a regular sinusoidal wave excitation force in simulation, the hydrodynamic forces are converted into a torque, emulated by a physical motor that is directly coupled with another identical physical DC machine as the generator. By utilizing the dSPACE Control Desk software and the associated dSPACE hardware, the control algorithm in the device uses a power electronics board to drive the machines. The results show that the control system applied to the hardware-in-the-loop framework can successfully extract energy for a scaled down version of the proposed WEC device.

16 TIDAL AND WAVE POWER↗

Mitigating Communication Delays in Remotely Connected Hardware-in-the-loop Experiments

Here, this paper introduces a potential approach for mitigating the effects of communication delays between multiple, closed-loop hardware-in-the-loop experiments which are virtually connected, yet physically separated. The method consists of an analytical method for the compensation of communication delays, along with the supporting computational and communication infrastructure. The control design leverages tools for the design of observers for the compensation of measurement errors in systems with time-varying delays. The proposed methodology is validated through computer simulation and hardware experimentation connecting hardware-in-the-loop experiments conducted between laboratories separated by a distance of over 100 km.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Performance Evaluation of Intelligent Solar Control Software Through Hardware-in-the-Loop (CRADA Final Report)

Recent research has highlighted the potential for solar to act as a zero-marginal-cost and zero-emission flexibility resource on the bulk power system when operated with advanced control systems. To increase the performance of these systems, leading technologies, including machine learning (ML) and hierarchical inverter set point allocation, have been developed by Latimer Controls, Inc. to estimate the headroom of large PV plants for grid operation and control; however, these technologies lack comprehensive validation under real-world application scenarios. Latimer Controls, Inc. received two voucher awards for research at a national laboratory from the Department of Energy American Made Solar Prize Round 6. The National Renewable Energy Laboratory (NREL) was selected to collaborate with Latimer staff to conduct a performance evaluation of Latimer PV control software. The NREL team will develop a hardware-in-the-loop (HIL) testbed to perform testing and validation of the Latimer PV control technology in a de-risked yet realistic testbed environment. Latimer and NREL worked together to analyze the test data, draw conclusions from the results, and disseminate the resulting scientific findings. In this CRADA work, we propose to test and validate the real-world application of the Latimer Control solution in an HIL environment. We evaluate the performance of different flexible solar technologies in responding to automatic generation control signals in a closed-loop fashion. In particular, a data-driven potential high limit (PHL) estimation is developed for large solar plants to accurately estimate their headroom so that they have fast and short-time regulation and control capability to participate in grid services and respond to grid signals in real time (e.g., AGC). This PHL estimation algorithm is embedded in a hardware power plant controller (PPC) and tested with an IEEE-39 bus system model developed in RTDS. To account for the varying cloud conditions and diverse inverter dispatches, we developed a 135-MW PV plant with detailed modeling of 27 individual PV modules and inverters using RTDS. The real-world communications used in such big plants, such as ModBus TCP/IP for inverter level and DNP3 for plant level, were developed to emulate the real-world applications in big PV plants. The ML-based PHL estimation method is tested under nine separate weather scenarios against the ‘reference-control’ solution, hereafter referred to as the baseline solution. The baseline method reserves a subset of inverters (reference group) to operate at their PHL at all times and dispatches only the remaining inverters (control group) at curtailed levels to fulfill the flexibility need. Despite being successfully piloted by NREL in California in 2017 and Chile in 2020, there exist two gaps in the state of the art to fully unlock the flexibility of PV plants: a. There is a trade-off between the PHL estimation accuracy and the flexibility range. b. There lacks granularity in the PHL estimation to capture the variation across inverters. The Latimer solution seeks to address these gaps by applying machine learning methods to improve PHL estimation accuracy while accounting for variability at every inverter. Performance metrics were taken from the 2023 Georgia Power CARES utility-scale RFP. The results demonstrate that the ML-based approach outperforms the traditional baseline method in PHL estimation accuracy for 7 of 9 scenarios. The average PHL error across the nine scenarios was 7.40% for the ML-based method, 2.06% less than the 9.46% PHL error average across scenarios that was exhibited by the baseline method. Additionally, the PHL error was below 5% for at least 95% of the testing interval for 3 of 9 tested intervals with the ML approach, whereas it did not achieve this metric for any of the baseline tests. Overall, simulation results indicate the superior performance of an ML-based approach compared to the conventional baseline reference-control approach, showcasing its potential to support grid stability and operational efficiency. This laboratory HIL testing using real PPC, representative power system simulation models in real-time with detailed PV plant and inverter models, and real-world communication protocols gives us confidence that this machine learning based PHL estimation algorithm works well in the hardware PPC and therefore de-risks future field commissioning. The end goal of this project is to advance grid technology to address the grid operation challenges brought by solar plant’s variability and uncertainties in power generation.

14 SOLAR ENERGY↗

A New Approach in Force-Limited Vibration Testing of Flight Hardware

The force-limited vibration test approaches discussed in NASA-7004C were developed to reduce overtesting associated with base shake vibration tests of aerospace hardware where the interface responses are excited coherently. This handbook outlines several different methods of specifying the force limits. The rationale for force limiting is based on the disparity between the impedances of typical aerospace mounting structures and the large impedances of vibration test shakers when the interfaces in general are coherently excited. Among these approaches, the semi-empirical method is presently the most widely used method to derive the force limits. The inclusion of the incoherent excitation of the aerospace structures at mounting interfaces has not been accounted for in the past and provides the basis for more realistic force limits for qualifying the hardware using shaker testing. In this paper current methods for defining the force limiting specifications discussed in the NASA handbook are reviewed using data from a series of acoustic and vibration tests. A new approach based on considering the incoherent excitation of the structural mounting interfaces using acoustic test data is also discussed. It is believed that the new approach provides much more realistic force limits that may further remove conservatism inherent in shaker vibration testing not accounted for by methods discussed in the NASA handbook. A discussion on using FEM/BEM analysis to obtain realistic force limits for flight hardware is provided.

force limiting responses↗

Micro Raman Spectroscopy for Characterizing Molecular Contamination on Space Flight Hardware

In the field of contamination control,many unknowns exist. Often, contamination control engineers have to utilize multiple spectroscopic, macroscopic, and microscopic tools to identify contamination sources when there is a potential contamination exposure to space flight hardware. Understanding the chemical composition of the molecular contamination provides an opportunity for contamination control engineers to determine if this contamination is problematic or benign. In this study, an existing witness plate program for monitoring space flight hardware during the assembly, integration, and testing phases is coupled with micro Raman spectroscopy analysis. The main goal of this study is to determine the limitations, reproducibility, and throughput of micro Raman spectroscopy for characterizing molecular contamination. Micro Raman Spectroscopy will be an additional tool used by contamination control engineers to monitor the cleanliness of space flight hardware.

Microscope↗