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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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This paper describes a programmable DSP-based testbed that is employed in the development and evaluation of blind demodulation algorithms to be used in wireless satellite or terrestrial communications systems.
PALM-3000 (P3K), the second-generation adaptive optics (AO) instrument for the 5.1 meter Hale telescope atPalomar Observatory, was released as a facility class instrument in October 2011 and has since been used on-skyfor over 600 nights as a workhorse science instrument and testbed for coronagraph and detector development.In late 2019 P3K underwent a significant upgrade to its wavefront sensor (WFS) arm and real-time control(RTC) system to reinforce its position as a state-of-the-art AO facility and extend its faint-end capability forhigh-resolution imaging and precision radial velocity follow-up of Kepler and TESS targets. The main featuresof this upgrade include an EM-CCD WFS camera capable of 3.5 kHz framerates, and an advanced Digital SignalProcessor (DSP) based RTC system to replace the aging GPU based system. Similar to the pre-upgrade system,the Shack-Hartmann wavefront sensor supports multiple pupil sampling modes using a motorized lenslet stage.The default sampling mode with 64×64 subapertures has been re-commissioned on-sky in late 2019, witha successful return to science observations in November 2019. In 64×mode the upgraded system is alreadyachieving K-band Strehl ratios up to 85% on-sky and can lock on natural guide stars as faint as mV=16. A16×16 subaperture mode is scheduled for on-sky commissioning in Fall 2020 and will extend the system’s faintlimit even further. Here we present the design and on-sky re-commissioning results of the upgraded system,dubbed P3K-II.
In 1978, Delayen showed how Self-Excited Loops (SEL) can be used to great advantage for controlling narrow-band SRF cavities. Its key capability is establishing closed-loop amplitude control early in the setup process, stabilizing Lorentz forces to allow cavity tuning and phase loop setup in a stable environment. As people around the world implement this basic idea with modern FPGA DSP technology, multiple variations and operational scenarios creep in that have both obvious and non-obvious ramifications for latency, feedback stability, and resiliency. This paper will review the key properties of a Delayen-style SEL when set up for open-loop, amplitude stabilized, and phase-stabilized modes. Then the original analog circuit will be compared and contrasted with the known variations of digital CORDIC-based implementations.
Indirect matrix converters (IMC) can offer high efficiency, high power density, and bidirectional power flow capability with a single-stage three-to single-phase AC-AC power conversion integrating a conventional three-phase active rectifier with a primary side full-bridge inverter of a dual active bridge converter. However, the IMCs generally require space vector modulation techniques, leading to complex sectors and dwell times calculations. A practical implementation of the modulation methods with a commonly used digital signal processor becomes even more challenging when considering power factor correction, harmonics reduction, and deadtime between sector transitions. This paper proposes a simple and robust carrier-based pulse width modulation (PWM) technique determined through a voltage-source inverter (VSI) to current-source inverter (CSI) to IMC conversion. This translation enables the adoption of all conventional VSI control methods with active and reactive power control in the IMCs through simple carrier and reference waveform comparison. The VSI vectors are first one-on-one matched with CSI vectors and translated to IMC modulation signals without calculating sectors and dwell times. Nine different carrier waveforms are proposed, and the converter performance is analyzed. Grid current THD and efficiency are estimated for each modulation method. The symmetric A and B methods had the lowest THD of the grid current, 2.80%, and the efficiency remained at approximately 98.3%, making it the most suitable carrier-based method proposed in this paper. The space vector PWM (SVPWM) modulation method was implemented to the DSP and generated the expected twelve gate signals.
The SuperCDMS SNOLAB dark matter search experiment aims to be sensitive to energy depositions down to Script O(1 eV). This imposes requirements on the resolution, signal efficiency, and noise rejection of the trigger system. To accomplish this, the SuperCDMS level-1 trigger system is implemented in an FPGA on a custom PCB. A time-domain optimal filter algorithm realized as a finite impulse response filter provides a baseline resolution of 0.38 times the standard deviation of the noise, σn, and a 99.9% trigger efficiency for signal amplitudes of 1.1 σ n in typical noise conditions. Embedded in a modular architecture, flexible trigger logic enables reliable triggering and vetoing in a dead-time-free manner for a variety of purposes and run conditions. The trigger architecture and performance are detailed in this article.
A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.
We introduce a technique to mitigate the effects of low frequency noise on precision timing. The example of Dark Count Noise Rate (DCR) in Silicon Photomultipliers (SiPMs) is emphasized. This technique exploits the correlation between time shifts on the leading edge of a signal and the residual slope of the baseline (due to noise) which remains after baseline subtraction. In fast timing applications (such as for Time-of-flight particle ID) the signal arrival time is typically captured on the signal leading edge. The signal risetime is often fixed by the physics of the sensor and input circuit. Then accurate pulse timing can be achieved by correcting a leading edge threshold time (depending on a slope proportional to both the Amplitude and the risetime) to a “constant fraction” time. This compensation for time walk due to amplitude fluctuations breaks down once we introduce interference from low frequency noise on the leading edge. In this paper we demonstrate that an additional measurement of the slope at threshold can be used to correct for this noise jitter.
Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.
For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function.
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The Earth Science Remote Access Tool (ESRAT) is an http-based application that facilitates internet access to user-defined subsets of Earth Science data.
A state-of-the-art digital Fourier Transform spectrometer has been developed, with a combination of high bandwidth and fine resolution unavailable elsewhere. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved Analog-to-Digital Converters (ADC). This 6 Gsps (giga sample per second) digital representation of the analog signal is then processed through an FPGA-based streaming Fast Fourier Transform (FFT), the key development described below. Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers. The implementation, results and underlying math for this spectrometer, as well as potential for future extension to even higher bandwidth, resolution and channel orthogonality, needed to support proposed future advanced atmospheric science and radioastronomy, are discussed.
No abstract available
Multirate (decimation/interpolation) filters are among the essential signal processing components in spaceborne instruments where Finite Impulse Response (FIR) filters are often used to minimize nonlinear group delay and finite-precision effects. Cascaded (multi-stage) designs of Multi-Rate FIR (MRFIR) filters are further used for large rate change ratio, in order to lower the required throughput while simultaneously achieving comparable or better performance than single-stage designs. Traditional representation and implementation of MRFIR employ polyphase decomposition of the original filter structure, whose main purpose is to compute only the needed output at the lowest possible sampling rate. In this paper, an alternative representation and implementation technique, called TD-MRFIR (Thread Decomposition MRFIR), is presented. The basic idea is to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition. Each thread represents an instance of the finite convolution required to produce a single output of the MRFIR. The filter is thus viewed as a finite collection of concurrent threads. The technical details of TD-MRFIR will be explained, first showing its applicability to the implementation of downsampling, upsampling, and resampling FIR filters, and then describing a general strategy to optimally allocate the number of filter taps. A particular FPGA design of multi-stage TD-MRFIR for the L-band radar of NASA's SMAP (Soil Moisture Active Passive) instrument is demonstrated; and its implementation results in several targeted FPGA devices are summarized in terms of the functional (bit width, fixed-point error) and performance (time closure, resource usage, and power estimation) parameters.
Solar Electric Propulsion (SEP) trajectories are shown for Mars missions between late 2004 and 2011.
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