SEARCH · Engineering Papers

Results for “Circuit simulation”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 253 records · Page 14

All sources NASA NTRS DOE OSTI

NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

4H-SiC nJFET↗

NASA NTRS1997

EOS-AM1 Nickel Hydrogen Cell Interim Life Test Report

This paper reports the interim results of the Earth Observing System AM-1 project (EOS-AM-1) nickel hydrogen cell life test being conducted under contract to National Aeronautics and Space Administration (NASA) Goddard Space Flight Center (GSFC) at the Lockheed Martin Missiles and Space (LMMS) facility in East Windsor, NJ; and at COMSAT Labs., Clarksburg, MD. The purpose of the tests is to verify that the EOS-AM-l cell design can meet five years of real-time Low Earth Orbit (LEO) cycling. The tests include both real-time LEO and accelerated stress tests. At LMMS, the first real-time LEO simulated 99 minute orbital cycle started on February 7, 1994 and the test has been running continuously since that time, with 13000 LEO cycles completed as of September 2, 1996. Each cycle consists of a 64 minute charge (VT at 1.507 volts per cell, 1.06 C/D ratio, followed by 0.6 ampere trickle charge) and a 35 minute constant power discharge at 177 watts (22.5% DOD). At COMSAT, the accelerated stress test consists of 90 minute orbital cycles at 60% DOD with a 30 minute discharge at 60 amperes and a 60 minute charge at 40 ampercs (VT at 1.54 volts per cell to 1.09 C/D ratio, followed by 0.6 ampere trickle charge). The real-time LEO life test battery consists of seven, 50AH (nameplate rating) Eagle-Picher, Inc. (EPI) Mantech cells manufactured into three, 3-cell pack assemblies (there are two place holder cells that are not part of the life test electrical circuit). The test pack is configured to simulate the conductive thermal design of the spacecraft battely, including: conductive aluminum sleeves, 3-cell pack aluminum baseplate, and honeycomb panel all mounted to a liquid (-5 C) cold plate. The entire assembly is located in a thermal chamber operating at +3 C. The accelerated stress test unit consists of five cells mounted in machined aluminum test sleeves and is operating at +10 C. The real-time LEO life test battery has met all performance requirements through the first 13,000 cycles, including: end of charge and discharge cell voltages and voltage gradients; end of chalge and discharge cell pressures; within cell and between cell temperature gradients; discharge capacity; current and power levels; and all chalge parameters. The accelerated stress test battely has completed over 5900 cycles as of 9/11/96. This paper reports both battery performances as a function of cycle life, with individual cell performance comparisons repolted for selected cycles in both tests.

Bennett, C. W.↗

NASA NTRS1999

EOS--AM1 Nickel Hydrogen Cell Interim Life Test Report

This paper reports the interim results of the Earth Observing System AM-1 project (EOS-AM-1) nickel hydrogen cell life test being conducted under contract to National Aeronautics and Space Administration (NASA) Goddard Space Flight Center (GSFC) at the Lockheed Martin Missiles and Space (LMMS) facility in East Windsor, NJ; and at COMSAT Labs., Clarksburg, MD. The purpose of the tests is to verify that the EOS-AM-1 cell design can meet five years of real-time Low Earth Orbit (LEO) cycling. The tests include both real-time LEO and accelerated stress tests. At LMMS, the first real-time LEO simulated 99 minute orbital cycle started on February 7, 1994 and the test has been running continuously since that time, with 18202 LEO cycles completed as of September 1, 1997. Each cycle consists of a 64 minute charge (VT at 1.507 volts per cell. 1.06 C/D ratio, followed by 0.6 ampere trickle charge) and a 35 minute constant power discharge at 177 watts (22.5% DOD). At COMSAT, the accelerated stress test consists of 90 minute orbital cycles at 60% DOD with a 30 minute discharge at 60 amperes and a 60 minute charge at 40 amperes (VT at 1.54 volts per cell to 1.09 C/D ratio, followed by 0.6 ampere trickle charge). The real-time LEO life test battery consists of seven, 50AH (nameplate rating) Eagle-Picher, Inc. (EPI) Mantech cells manufactured into three. 3-cell pack assemblies (there are two place holder cells that are not part of the life test electrical circuit). The test pack is configured to simulate the conductive thermal design of the spacecraft battery, including: conductive aluminum sleeves, 3-cell pack aluminum baseplate, and honeycomb panel all mounted to a liquid (-5 C) cold plate. The entire assembly is located in a thermal chamber operatina at +30 C. The accelerated stress test unit consists of five cells mounted in machined aluminum test sleeves and is operating at +10 C. The real-time LEO life test battery has met all performance requirements throuch the first 18,202 cycles, including: end of chargee and discharge cell voltages and voltace -radients; end of charge and discharge cell pressures; within cell and between cell temperature gradients; discharge capacity; current and power levels; and all charge parameters. The accelerated stress test battery has completed 11,998 cycles when the test was terminated. The stress test unit met all test parameters. This paper reports battery performances as a function of cycle life for both the real time LEO and the accelerated life test regimes.

Bennett, C. W.↗

NASA NTRS1997

EOS-AM1 Nickel Hydrogen Cell

This paper reports the interim results of the Earth Observing System AM-1 project (EOS-AM-1) nickel hydrogen cell life test being conducted under contract to National Aeronautics and Space Administration (NASA) Goddard Space Flight Center (GSFC) at the Lockheed Martin Missile and Space (LMMS) facility in East Windsor, NJ; and at COMSAT Labs., Clarksburg, MD. The purpose of die tests is to verify that the EOS-AM-1 cell design can meet five years of real-time Low Earth Orbit (LEO) cycling. The tests include both real-time LEO and accelerated stress tests. At LMMS, the first real-time LEO simulated 99 minute orbital cycle started on February 7, 1994 and the test has been running continuously since that time, with 18,202 LEO cycles completed as of September 1, 1997. Each cycle consists of a 64 minute charge (VT at 1.507 volts per cell, 1.06 C/D ratio, followed by 0.6 ampere trickle charge) and a 35 minute constant power discharge at 177 watts (22.5% DOD). At COMSAT, the accelerated stress test consists of 90 minute orbital cycles at 60% DOD with a 30 minute discharge at 60 amperes and a 60 minute charge at 40 amperes (VT at 1.54 volts per cell to 1.09 C/D ratio, followed by 0.6 ampere trickle charge). The real-time LEO life test battery consists of seven, 50AH (nameplate rating) Eagle-Picher, Inc. (EPI) Mantech cells manufactured into three, 3-cell pack assemblies (there are two place holder cells that are not part of the life test electrical circuit). The test pack is configured to simulate the conductive thermal design of the spacecraft battery, including: conductive aluminum sleeves, 3-cell pack aluminum baseplate, and honeycomb panel all mounted to a liquid (-5 C) cold plate. The entire assembly is located in a thermal chamber operating at +30 C. The accelerated stress test unit consists of five cells mounted in machined aluminum test sleeves and is operating at +10 C. The real-time LEO life test battery has met all performance requirements through the first 18,202 cycles, including: end of charge mid discharge cell voltages and voltage gradients; end of charge and discharge cell pressures; within cell and between cell temperature gradients; discharge capacity; current and power levels; and all charge parameters. The accelerated stress test battery has completed 11,998 cycles when the test was terminated. The stress test unit met all test parameters. This paper reports battery perfortnances as a funcfion of cycle life for both the real-time LEO and the accelerated life test regimes.

Bennett, Charles W.↗

NASA NTRS1998

EOS-AM1 Nickel Hydrogen Cell Interim Life Test Report

This paper reports the interim results Earth Observing System AM-1 project (EOS-AM-1) nickel hydrogen cell life test being conducted under contract to National Aeronautics and Space Administration (NASA) Goddard Space Flight Center (GSFC) at the Lockheed Martin Missiles and Space (LMMS) facility in East Windsor, NJ; and at COMSAT Labs., Clarksburg, MD. The purpose of the tests is to verify that the EOS-AM-1 cell design can meet five years of real-time Low Earth Orbit (LEO) cycling. The tests include both real-time LEO and accelerated stress tests. At LMMS, the first real-time LEO simulated 99 minute orbital cycle started on February 7, 1994 and the test has been running continuously since that time, with 18202 LEO cycles completed as of September 1, 1997. Each cycle consists of a 64-minute charge (VT at 1,507 volts per cell, 1.06 C/D ratio, followed by 0.6 ampere trickle charge) and a 35 minute constant power discharge at 177 watts (22.5 percent DOD). At COMSAT, the accelerated stress test consists of 90 minute orbital cycles at 60 percent DOD with a 30 minute discharge at 60 amperes and a 60 minute charge at 40 amperes (VT at 1.54 volts per cell to 1.90 C/D ratio, followed by 0.6 ampere trickle charge). The real-time LEO life test battery consists of seven, 50AH (nameplate rating) Eagle-Picher, Inc. (EPI) Mantech cells manufactured into three, 3-cell pack assemblies (there are two place holder cells that are not part of the life test electrical circuit). The test pack is configured to simulate the conductive thermal design of the spacecraft battery, including: conductive aluminum sleeves, 3-cell pack aluminum baseplate, and honeycomb panel all mounted to a liquid (minus 5 deg) cold plate. The entire assembly is located in a thermal chamber operating at plus 3 deg. The accelerated stress test unit consists of five cells mounted in machined aluminum test sleeves and is operating at plus 10 deg. The real-time LEO life test battery has met all performance requirements through the first 18,202 cycles, including: end of charge and discharge cell voltages and voltage gradients; end of charge and discharge cells pressures; within cell and between cell temperature gradients dischare capacity; current and power levels; and all charge parameters. The accelerated stress test battery has completed 11998 cycles when the test was terminated. The stress test unit met all test parameters. This paper reports battery performances as a function of cycle life for both the real-time LEO and the accelerated life test regimes.

Bennett, Charles W.↗

NASA NTRS2011

Modeling from Local to Subsystem Level Effects in Analog and Digital Circuits Due to Space Induced Single Event Transients

Single Event Transients in analog and digital electronics from space generated high energetic nuclear particles can disrupt either temporarily and sometimes permanently the functionality and performance of electronics in space vehicles. This work first provides some insights into the modeling of SET in electronic circuits that can be used in SPICE-like simulators. The work is then directed to present methodologies, one of which was developed by this author, for the assessment of SET at different levels of integration in electronics, from the circuit level to the subsystem level.

State Transistion Model.↗

NASA NTRS1977

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Stahl, R. H.↗

NASA NTRS1979

Power combining in an array of microwave power rectifiers

This work analyzes the resultant efficiency degradation when identical rectifiers operate at different RF power levels as caused by the power beam taper. Both a closed-form analytical circuit model and a detailed computer-simulation model are used to obtain the output dc load line of the rectifier. The efficiency degradation is nearly identical with series and parallel combining, and the closed-form analytical model provides results which are similar to the detailed computer-simulation model.

Gutmann, R. J.↗

NASA NTRS1984

Electrical System Technology Working Group (WG) Report

The technology needs for space power systems (military, public, commercial) were assessed for the period 1995 to 2005 in the area of power management and distribution, components, circuits, subsystems, controls and autonomy, modeling and simulation. There was general agreement that the military requirements for pulse power would be the dominant factor in the growth of power systems. However, the growth of conventional power to the 100 to 250kw range would be in the public sector, with low Earth orbit needs being the driver toward large 100kw systems. An overall philosophy for large power system development is also described.

Silverman, S.↗

NASA NTRS1991

Formal hardware verification of digital circuits

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

Joyce, J.↗

NASA NTRS1992

Analog/digital pH meter system I.C.

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Vincent, Paul↗

NASA NTRS1999

Experimental Verification of the Use of Metal Filled Via Hole Fences for Crosstalk Control of Microstrip Lines in LTCC Packages

Coupling between microstrip lines in dense RF packages is a common problem that degrades circuit performance. Prior 3D-FEM electromagnetic simulations have shown that metal filled via hole fences between two adjacent microstrip lines actually increases coupling between the lines; however, if the top of the via posts are connected by a metal Strip, coupling is reduced. In this paper, experimental verification of the 3D-FEM simulations Is demonstrated for commercially fabricated LTCC packages.

Ponchak, George E.↗

NASA NTRS2005

A Study of the Measurement of Seebeck Coefficient of SiGe

In 1821 German Physicist Thomas J. Seebeck discovered that heat could be converted into electricity when a temperature difference was applied across two points on a material. Theoretically, the generated voltage has a directly proportional relationship with the temperature difference. This relationship is the Seebeck coefficient that scientists always referred to when determining the efficiency of a thermoelectricity convention. In our experiments, however, hysteresis loops appeared when we plotted voltage against temperature difference, and the measured Seebeck appeared differently when the measurements were run under vacuum, air, and helium gas. Measurements were done by using a low-frequency AC measuring method. By simulating the experimental setup into a; thermal circuit, we found that the loop and inconsistency in measuring Seebeck coefficient could be explained by studying the behaviors of a RC circuit in a thermal sense. Under vacuum, the gap of the hysteresis loop can be largely eliminated if the time period of the temperature difference increased up to 4800s. The trend of the variations in measuring Seebeck coefficients in different environments can also be predicted by using different thermal circuit models.

Heung, King Yi↗

NASA NTRS2004

THz semiconductor-based front-end receiver technology for space applications

Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

Schottky diode multipliers↗

NASA NTRS2011

A Background Noise Reduction Technique Using Adaptive Noise Cancellation for Microphone Arrays

Background noise in wind tunnel environments poses a challenge to acoustic measurements due to possible low or negative Signal to Noise Ratios (SNRs) present in the testing environment. This paper overviews the application of time domain Adaptive Noise Cancellation (ANC) to microphone array signals with an intended application of background noise reduction in wind tunnels. An experiment was conducted to simulate background noise from a wind tunnel circuit measured by an out-of-flow microphone array in the tunnel test section. A reference microphone was used to acquire a background noise signal which interfered with the desired primary noise source signal at the array. The technique s efficacy was investigated using frequency spectra from the array microphones, array beamforming of the point source region, and subsequent deconvolution using the Deconvolution Approach for the Mapping of Acoustic Sources (DAMAS) algorithm. Comparisons were made with the conventional techniques for improving SNR of spectral and Cross-Spectral Matrix subtraction. The method was seen to recover the primary signal level in SNRs as low as -29 dB and outperform the conventional methods. A second processing approach using the center array microphone as the noise reference was investigated for more general applicability of the ANC technique. It outperformed the conventional methods at the -29 dB SNR but yielded less accurate results when coherence over the array dropped. This approach could possibly improve conventional testing methodology but must be investigated further under more realistic testing conditions.

Spalt, Taylor B.↗

NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗

NASA NTRS2002

On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

Stoica, Adrian↗