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Results for “Circuit depth”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14

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NASA NTRS1991

Coaxial line configuration for microwave power transmission study of YBa2Cu3O(7-delta) thin films

Microwave transmission measurements through YBa2Cu3O(7-delta) (YBCO) high-transition-temperature superconducting thin films on lanthanum aluminate (LaAlO3) have been performed in a coaxial line at 10 GHz. LaAlO3 substrates were ultrasonically machined into washer-shaped discs, polished, and coated with laser-ablated YBCO. These samples were mounted in a 50-ohm coaxial air line to form a short circuit. The power transmitted through the films as a function of temperature was used to calculate the normal state conductivity and the magnetic penetration depth for the films.

Chorey, C. M.↗

NASA NTRS2003

Preparation of Regular Specimens for Atom Probes

A method of preparation of specimens of non-electropolishable materials for analysis by atom probes is being developed as a superior alternative to a prior method. In comparison with the prior method, the present method involves less processing time. Also, whereas the prior method yields irregularly shaped and sized specimens, the present developmental method offers the potential to prepare specimens of regular shape and size. The prior method is called the method of sharp shards because it involves crushing the material of interest and selecting microscopic sharp shards of the material for use as specimens. Each selected shard is oriented with its sharp tip facing away from the tip of a stainless-steel pin and is glued to the tip of the pin by use of silver epoxy. Then the shard is milled by use of a focused ion beam (FIB) to make the shard very thin (relative to its length) and to make its tip sharp enough for atom-probe analysis. The method of sharp shards is extremely time-consuming because the selection of shards must be performed with the help of a microscope, the shards must be positioned on the pins by use of micromanipulators, and the irregularity of size and shape necessitates many hours of FIB milling to sharpen each shard. In the present method, a flat slab of the material of interest (e.g., a polished sample of rock or a coated semiconductor wafer) is mounted in the sample holder of a dicing saw of the type conventionally used to cut individual integrated circuits out of the wafers on which they are fabricated in batches. A saw blade appropriate to the material of interest is selected. The depth of cut and the distance between successive parallel cuts is made such that what is left after the cuts is a series of thin, parallel ridges on a solid base. Then the workpiece is rotated 90 and the pattern of cuts is repeated, leaving behind a square array of square posts on the solid base. The posts can be made regular, long, and thin, as required for samples for atom-probe analysis. Because of their small volume and regularity, the amount of FIB-milling time can be much less than that of the method of sharp shards. Individual posts can be broken off for mounting in a manner similar to that of the method of sharp shards. Alternatively, the posts can be left intact on the base and the base can be cut to a small square (e.g., 3 by 3 mm) suitable for mounting in an atom probe of a type capable of accepting multiple-tip specimens. The advantage of multiple-tip specimens is the possibility of analyzing many tips without the time-consuming interchange of specimens.

Kuhlman, Kim↗

DOE OSTI2026

Cathodic Protection Modeling for Hanford Underground Double-Shell Tank Farms

Hanford stores millions of gallons of radioactive and chemically hazardous waste from the production of weapon materials in tank farms consisting of underground carbon-steel storage tanks surrounded by reinforced concrete. Six of these Hanford tank farms use double-shell storage tanks (DSTs). The DST farms were constructed from 1968 to 1986 with a planned 40–50 year design life, so some are already operating beyond their initial life expectancy. Ultrasonic testing (UT) has indicated significant thinning on the bottom of the secondary (outer) liner of these tanks, believed to arise from groundwater intrusion driving concrete side corrosion. There is no direct access to the steel/concrete interface between the tank and the concrete pad, making it difficult to apply a chemical-based mitigation strategy or to conduct repairs, but cathodic protection (CP) is a possible method to inhibit further concrete-side corrosion. Hanford already uses CP to protect below grade steel piping within the tank farms and connected to the tanks, but this system was not designed to protect the tank bottoms. CP design must account for the structures surrounding the DSTs, including the steel reinforcing bars (rebar) within the concrete pad and vault, various process lines, and the existing CP system. In this study, finite element analysis (FEA) modeling was carried out to simulate CP protection of 1) a single tank and CP anode to develop options for modeling the rebar and to compare to a simpler circuit model and 2) the entire Hanford AN tank farm as a representative example consisting of seven tanks, associated piping, and both existing and new CP anodes. Both circuit and FEA models predict that significant protective current could be delivered to the bottoms of the tanks with the addition of tank-protection anodes below the depth of the tanks. Simulations with only the existing pipe-protection anodes active confirmed that only a very small current to the tank bottoms is predicted under present conditions. Multiple simplified representations of the dome and wall rebar were tested to reduce the computational complexity of the tank-farm simulations, resulting in modeling the rebar as edge elements with a prescribed effective circumference that matches the real rebar surface area. The geometry of the rebar is also simplified into horizontal hoops around the tank walls and radial rebar over the dome with increased effective circumference to retain the target surface area. This simplification was found to greatly reduce the complexity and solution time of the models without large changes in current distributions, especially to the tank bottom. A range of values were tested for model parameters such as soil and concrete resistivities and polarization resistance to investigate their impact on the current and electric potential distributions. Depending on the parameters used, FEA simulations predict some risk of overprotection, particularly on the piping system; since overprotection can also lead to surface damage associated with hydrogen gas generation at the interface (e.g. hydrogen embrittlement or damage to coatings), this needs to be considered when refining the design of the new CP system. Comparison between the FEA models and the circuit model representation demonstrated that the circuit model could not match the predicted FEA current distribution, even when using the exact same surface areas. This discrepancy appeared to be at least partly attributable to the impact of the relative positions of the tank components and anodes to each other and to the ground surface. The FEA model accounts for the relative positions since it solves the governing equations in three dimensions, but the circuit model cannot account for the positioning. In particular, the circuit model underpredicts the current to the tank bottom and overpredicts the current to the dome compared to FEA for the baseline geometry. The FEA models omitted the electrically isolated rebar in the bottom concrete slab. However, a circuit based stray current model estimated that only 2.1% of the total current through the slab would stray into the rebar, corresponding to ~0.21 A for a target current density of 2 mA/ft2 to the tank bottom. The estimated corrosion driven by this amount of stray current is predicted to yield a lifetime of >400 years for the minimum rebar diameter, assuming an acceptable cross-section area loss of 10%.

d'Entremont, Anna [Savannah River National Laborat↗

DOE OSTI2021

Dielectric screening in perovskite photovoltaics

Abstract The performance of perovskite photovoltaics is fundamentally impeded by the presence of undesirable defects that contribute to non-radiative losses within the devices. Although mitigating these losses has been extensively reported by numerous passivation strategies, a detailed understanding of loss origins within the devices remains elusive. Here, we demonstrate that the defect capturing probability estimated by the capture cross-section is decreased by varying the dielectric response, producing the dielectric screening effect in the perovskite. The resulting perovskites also show reduced surface recombination and a weaker electron-phonon coupling. All of these boost the power conversion efficiency to 22.3% for an inverted perovskite photovoltaic device with a high open-circuit voltage of 1.25 V and a low voltage deficit of 0.37 V (a bandgap ~1.62 eV). Our results provide not only an in-depth understanding of the carrier capture processes in perovskites, but also a promising pathway for realizing highly efficient devices via dielectric regulation.

14 SOLAR ENERGY↗

DOE OSTI2023

Transient Photocurrent From High-Voltage Vertical GaN Diodes Irradiated With Electrons: Experiments and Simulations

Radiation-hard high-voltage vertical GaN p-n diodes are being developed for use in power electronics subjected to ionizing radiation. Here, we present a comparison of the measured and simulated photocurrent response of diodes exposed to ionizing irradiation with 70 keV and 20 MeV electrons at dose rates in the range of 1.4x10 7 - 5.0x10 8 rad(GaN)/s. The simulations correctly predict the trend in measured steady-state photocurrent and agree with experimental results within a factor of 2. Furthermore, simulations of the transient photocurrent response to dose rates with uniform and non-uniform ionization depth profiles uncover the physical processes involved that cannot be otherwise experimentally observed due to orders of magnitude larger RC time constant of the test circuit. The simulations were performed using an Exploratory Physics Development code developed at Sandia National Laboratories. The code offers the capability to include defect physics under more general conditions, not included in commercially available software packages, extending the applicability of the simulations to different types of radiation environments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS1976

Hardware additions to microprocessor architecture aid software development

An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.

Sievers, M. W.↗

NASA NTRS1984

An in-depth review of photovoltaic system performance models

The features, strong points and shortcomings of 10 numerical models commonly applied to assessing photovoltaic performance are discussed. The models range in capabilities from first-order approximations to full circuit level descriptions. Account is taken, at times, of the cell and module characteristics, the orientation and geometry, array-level factors, the power-conditioning equipment, the overall plant performance, O and M effects, and site-specific factors. Areas of improvement and/or necessary extensions are identified for several of the models. Although the simplicity of a model was found not necessarily to affect the accuracy of the data generated, the use of any one model was dependent on the application.

Smith, J. H.↗

DOE OSTI2021

Ion beam mill etch depth monitoring with nanometer-scale resolution

A method for measuring conductance of a material real-time during etching/milling includes providing a fixture having a socket for receiving the material. The socket is attached to a printed circuit board (PCB) mounted on one side of a plate that has at least one opening for providing ion beam access to the material sample. Conductive probes extend from the other side of the PCB to contact and span a target area of the material. A measurement circuit in electrical communication with the probes measures the voltage produced when a current is applied across the material sample to measure changes in electrical properties of the sample over time.

Cybart, Shane A.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, H. T.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

Lin, Shu↗

DOE OSTI2023

Pairwise‐Parallel Entangling Gates on Orthogonal Modes in a Trapped‐Ion Chain

Abstract Parallel operations are important for both near‐term quantum computers and larger‐scale fault‐tolerant machines because they reduce execution time and qubit idling. This study proposes and implements a pairwise‐parallel gate scheme on a trapped‐ion quantum computer. The gates are driven simultaneously on different sets of orthogonal motional modes of a trapped‐ion chain. This work demonstrates the utility of this scheme by creating a Greenberger‐Horne‐Zeilinger (GHZ) state in one step using parallel gates with one overlapping qubit. It also shows its advantage for circuits by implementing a digital quantum simulation of the dynamics of an interacting spin system, the transverse‐field Ising model. This method effectively extends the available gate depth by up to two times with no overhead when no overlapping qubit is involved, apart from additional initial cooling. This scheme can be easily applied to different trapped‐ion qubits and gate schemes, broadly enhancing the capabilities of trapped‐ion quantum computers.

Optics↗

DOE OSTI2025

Performance evaluations of signed and unsigned noisy approximate quantum Fourier arithmetic

The Quantum Fourier Transform (QFT) grants competitive advantages, especially in resource usage and circuit approximation, for performing arithmetic operations on quantum computers, and offers a potential route toward a numerical quantum-computational paradigm. In this paper, we utilize efficient techniques to implement QFT-based integer addition and multiplications. These operations are fundamental to various quantum applications including Shor’s algorithm, weighted-sum optimization problems in data processing and machine learning, and quantum algorithms requiring inner products. We carry out performance evaluations of these implementations based on IBM’s superconducting-qubit architecture using different compatible noise models. We isolate the sensitivity of the component quantum circuits on both one-/two-qubit gate error rates, and the number of the arithmetic operands’ superposed integer states. We analyze performance and identify the most effective approximation depths for unsigned quantum addition and quantum multiplication within the given context. We then perform a similar analysis of signed addition and compare to the unsigned results. We observe significant dependency of the optimal approximation depth on the degree of machine noise and the number of superposed states in certain performance regimes. Finally, we elaborate on the algorithmic challenges—relevant to signed, unsigned, modular and non-modular versions—that could also be applied to current implementations of QFT-based subtraction, division, exponentiation, and their potential tensor extensions. Here, we analyze the performance trends in our results and speculate on possible future developments within this computational paradigm.

Computational models↗

DOE OSTI2022

Performance Evaluations of Noisy Approximate Quantum Fourier Arithmetic

The Quantum Fourier Transform (QFT) grants competitive advantages, especially in resource usage and circuit approximation, for performing arithmetic operations on quantum computers, and offers a potential route towards a numerical quantum-computational paradigm. In this paper, we utilize efficient techniques to implement QFT-based integer addition and multiplications. These operations are fundamental to various quantum applications including Shor’s algorithm, weighted sum optimization problems in data processing and machine learning and quantum algorithms requiring inner products. We carry out performance evaluations of these implementations based on IBM’s superconducting qubit architecture using different compatible noise models. We isolate the sensitivity of the component quantum circuits on both one-/two-qubit gate error rates, and the number of the arithmetic operands’ superposed integer states. We analyze performance, and identify the most effective approximation depths for quantum add and quantum multiply within the given context. We observe significant dependency of the optimal approximation depth on the degree of machine noise and the number of superposed states in certain performance regimes. Finally, we elaborate on the algorithmic challenges - relevant to signed, unsigned, modular and non-modular versions - that could also be applied to current implementations of QFT-based subtraction, division, exponentiation, and their potential tensor extensions. Here, we analyze performance trends in our results and speculate on possible future development within this computational paradigm.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2001

System for Measuring Capacitance

A system has been developed for detecting the level of a liquid in a tank wherein a capacitor positioned in the tank has spaced plates which are positioned such that the dielectric between the plates will be either air or the liquid, depending on the depth of the liquid in the tank. An oscillator supplies a sine wave current to the capacitor and a coaxial cable connects the capacitor to a measuring circuit outside the tank. If the cable is very long or the capacitance to be measured is low, the capacitance inherent in the coaxial cable will prevent an accurate reading. To avoid this problem, an inductor is connected across the cable to form with the capacitance of the cable a parallel resonant circuit. The impedance of the parallel resonant circuit is infinite, so that attenuation of the measurement signal by the stray cable capacitance is avoided.

McNichol, Randal S.↗

NASA NTRS1997

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, Hari T.↗

DOE OSTI2020

Roles of bandgrading, lifetime, band alignment, and carrier concentration in high-efficiency CdSeTe solar cells

CdSeTe alloying has significantly increased the efficiency of CdTe-based solar technology. Here, computational modeling compares how different CdSeTe bandgrading, carrier lifetimes, band alignment, and carrier concentrations contribute to transport, recombination, and performance. We find that the gain in photocurrent caused by bandgap narrowing alone is insufficient to describe experimental efficiency gains. Performance can be increased by adjusting CdSeTe compositions and bandgrading depths. However, these performance gains are small relative to the contributions of enhanced lifetime by Se alloying, which can explain record cell efficiency gains with minimal open-circuit voltage loss despite significant bandgap narrowing. Similarly, CdSeTe band alignment shifts can significantly increase performance if front interface recombination is prevalent. For a wide range of CdSeTe grading profiles, the hole density is a critical component to achieve efficiencies exceeding 25%.

36 MATERIALS SCIENCE↗

NASA NTRS1980

Screen printing technology applied to silicon solar cell fabrication

The process for producing space qualified solar cells in both the conventional and wraparound configuration using screen printing techniques was investigated. Process modifications were chosen that could be easily automated or mechanized. Work was accomplished to optimize the tradeoffs associated with gridline spacing, gridline definition and junction depth. An extensive search for possible front contact metallization was completed. The back surface field structures along with the screen printed back contacts were optimized to produce open circuit voltages of at least an average of 600 millivolts. After all intended modifications on the process sequence were accomplished, the cells were exhaustively tested. Electrical tests at AMO and 28 C were made before and after boiling water immersion, thermal shock, and storage under conditions of high temperature and high humidity.

Thornhill, J. W.↗

NASA NTRS1985

Processing technology for high efficiency silicon solar cells

Recent advances in silicon solar cell processing have led to attainment of conversion efficiency approaching 20%. The basic cell design is investigated and features of greatest importance to achievement of 20% efficiency are indicated. Experiments to separately optimize high efficiency design features in test structures are discussed. The integration of these features in a high efficiency cell is examined. Ion implantation has been used to achieve optimal concentrations of emitter dopant and junction depth. The optimization reflects the trade-off between high sheet conductivity, necessary for high fill factor, and heavy doping effects, which must be minimized for high open circuit voltage. A second important aspect of the design experiments is the development of a passivation process to minimize front surface recombination velocity. The manner in which a thin SiO2 layer may be used for this purpose is indicated without increasing reflection losses, if the antireflection coating is properly designed. Details are presented of processing intended to reduce recombination at the contact/Si interface. Data on cell performance (including CZ and ribbon) and analysis of loss mechanisms are also presented.

Spitzer, M. B.↗