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At least 253 records · Page 14

Methods for growth of relatively large step-free SiC crystal surfaces

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Neudeck, Philip G.↗

Method for the growth of large low-defect single crystals

A method and the benefits resulting from the product thereof are disclosed for the growth of large, low-defect single-crystals of tetrahedrally-bonded crystal materials. The process utilizes a uniquely designed crystal shape whereby the direction of rapid growth is parallel to a preferred crystal direction. By establishing several regions of growth, a large single crystal that is largely defect-free can be grown at high growth rates. This process is particularly suitable for producing products for wide-bandgap semiconductors, such as SiC, GaN, AlN, and diamond. Large low-defect single crystals of these semiconductors enable greatly enhanced performance and reliability for applications involving high power, high voltage, and/or high temperature operating conditions.

Powell, J. Anthony↗

NASA Tech Briefs, December 2006

Topic include: Inferring Gear Damage from Oil-Debris and Vibration Data; Forecasting of Storm-Surge Floods Using ADCIRC and Optimized DEMs; User Interactive Software for Analysis of Human Physiological Data; Representation of Serendipitous Scientific Data; Automatic Locking of Laser Frequency to an Absorption Peak; Self-Passivating Lithium/Solid Electrolyte/Iodine Cells; Four-Quadrant Analog Multipliers Using G4-FETs; Noise Source for Calibrating a Microwave Polarimeter; Hybrid Deployable Foam Antennas and Reflectors; Coating MCPs with AlN and GaN; Domed, 40-cm-Diameter Ion Optics for an Ion Thruster; Gesture-Controlled Interfaces for Self-Service Machines; Dynamically Alterable Arrays of Polymorphic Data Types; Identifying Trends in Deep Space Network Monitor Data; Predicting Lifetime of a Thermomechanically Loaded Component; Partial Automation of Requirements Tracing; Automated Synthesis of Architecture of Avionic Systems; SSRL Emergency Response Shore Tool; Wholly Aromatic Ether-Imides as n-Type Semiconductors; Carbon-Nanotube-Carpet Heat-Transfer Pads; Pulse-Flow Microencapsulation System; Automated Low-Gravitation Facility Would Make Optical Fibers; Alignment Cube with One Diffractive Face; Graphite Composite Booms with Integral Hinges; Tool for Sampling Permafrost on a Remote Planet; and Special Semaphore Scheme for UHF Spacecraft Communications.

Source record↗

Microstructural and Mechanical Evaluation of a Cu-Based Active Braze Alloy to Join Silicon Nitride Ceramics

Self-joining of St. Gobain Si3N4 (NT-154) using a ductile Cu-Al-Si-Ti active braze (Cu-ABA) was demonstrated. A reaction zone approx.2.5-3.5 microns thick) developed at the interface after 30 min brazing at 1317 K. The interface was enriched in Ti and Si. The room temperature compressive shear strengths of Si3N4/Si3N4 and Inconel/Inconel joints (the latter created to access baseline data for use with the proposed Si3N4/Inconel joints) were 140+/-49MPa and 207+/-12MPa, respectively. High-temperature shear tests were performed at 1023K and 1073 K, and the strength of the Si3N4/Si3N4 and Inconel/Inconel joints were determined. The joints were metallurgically well-bonded for temperatures above 2/3 of the braze solidus. Scanning and transmission electron microscopy studies revealed a fine grain microstructure in the reaction layer, and large grains in the inner part of the joint with interfaces being crack-free. The observed formation of Ti5Si3 and AlN at the joint interface during brazing is discussed.

Singh, M.↗

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

Zheng, Xinyu↗

AIN-Based Packaging for SiC High-Temperature Electronics

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Savrun, Ender↗

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗

Low Temperature Flux Growth of 2H-SiC and Beta-Gallium Oxide

We present brief overview of our study on the low temperature flux growth of two very important novel wide bandgap materials 2H-SiC and Beta-gallium oxide (Beta-Ga2O3). We have synthesized and grown 5 millimeter to 1 centimeter size single crystals of Beta-gallium oxide (Beta-Ga2O3). We used a flux and semi wet method to grow transparent good quality crystals. In the semi-wet method Ga2O3 was synthesized with starting gallium nitrate solution and urea as a nucleation agent. In the flux method we used tin and other metallic flux. This crystal was placed in an alumina crucible and temperature was raised above 1050 degrees Centigrade. After a time period of thirty hours, we observed prismatic and needle shaped crystals of gallium oxide. Scanning electron microscopic studies showed step growth morphology. Crystal was polished to measure the properties. Bandgap was measured 4.7electronvolts using the optical absorption curve. Another wide bandgap hexagonal 2H-SiC was grown by using Si-Al eutectic flux in the graphite crucible. We used slight AlN also as the impurity in the flux. The temperature was raised up to 1050 degrees Centigrade and slowly cooled to 850 degrees Centigrade. Preliminary characterization results of this material are also reported.

Singh, N. B.↗

Intermediate Temperature Ceramic Heat Pipe Modeling and Optimization

Spacecraft nuclear electric propulsion, as well as other emerging technologies, can benefit from heat pipes with optimal performance in the intermediate temperature, 450–700 K, regime. In this work, a 1D model was developed to investigate the performance of halide working fluids coupled with 3D printed-ceramic shells to operate at 500–600 K and interface with a nuclear electric propulsion system. An initial conceptual design and performance limits of a 3D printed-AlN heat pipe radiator with AlBr 3 as the working fluid is presented. An areal density of 5.2 kg/m 2 and mass per unit heat performance of 1.00kg/kW is estimated.

thermal management↗

Tailoring Growth Interfaces of Virtual Substrates for Power Electronics

Power electronics materials are poised to play a critical role in fulfilling next generation energy needs, with up to 90% of future energy demand predicted to flow through power electronics at some point.[1] Among a number of candidate materials, AlxGa1-xN is the strongest, having bipolar dopability, thermal and chemical stability, an ultra-wide bandgap, and demonstrated experimental feasibility. However, AlGaN growth is limited by a lack of lattice-matched substrates, ultimately stunting material quality at higher thicknesses needed for power electronics applications. Further, high power applications increasingly call for fully vertical device structures, necessitating a conductive substrate. [1] Recently our group identified the (111) plane of TaC as a conductive surface lattice-matched to Al0.55Ga0.45N, taking inspiration from prior work of AlN and GaN binaries on carbide and boride substrates. [2,3,4] In this talk we demonstrate the growth of (111)-oriented TaC by RF sputtering. We investigate the interface of TaC with sapphire and SiC substrates and identify means to suppress competing Ta2C nucleation in order to stabilize (111)-oriented TaC. Potential stacking sequences are identified with respect to crystal structure and observed twinning in the TaC films. We next assess structural changes and film recrystallization that results from face-to-face annealing of TaC thin films at high temperatures above 1500 degrees Celsius. Changes to grain structure and domain size are assessed by x-ray diffraction and surface morphology is explored using atomic force microscopy. Figure 1 shows significant improvements to in- and out-of-plane strain following annealing along with the formation of terraced step edges at the film surface. Strain as a function of material composition and thickness is considered, as this may play a major role in future nucleation of AlGaN layers.

CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SU↗

Tailoring Growth Interfaces of Virtual Substrates for Power Electronics

Power electronics materials are poised to play a critical role in fulfilling next generation energy needs, with up to 90% of future energy demand predicted to flow through power electronics at some point. AlxGa1-xN ranks high among candidate materials, having bipolar dopability, thermal and chemical stability and an ultra-wide bandgap. However, AlGaN growth is limited by a lack of lattice-matched substrates, ultimately stunting material quality at higher thicknesses needed for power electronics applications. Further, high power applications increasingly call for fully vertical device structures, necessitating a conductive substrate. Recently our group identified the (111) plane of TaC as a conductive surface lattice-matched to Al0.55Ga0.45N, taking inspiration from prior work of AlN and GaN binaries on carbide and boride substrates. In this talk we demonstrate the growth of (111)-oriented TaC by RF sputtering. We investigate the interface of TaC with sapphire and SiC substrates and identify means to suppress competing Ta2C nucleation in order to stabilize (111)-oriented TaC. Potential stacking sequences are identified with respect to crystal structure and observed twinning in the TaC films. We next assess structural changes and film recrystallization that results from face-to-face annealing of TaC thin films at high temperatures above 1500 degrees C. Changes to grain structure and domain size are assessed by x-ray diffraction and surface morphology is explored using atomic force microscopy. Figure 1 shows significant improvements to in- and out-of-plane strain following annealing along with the formation of terraced step edges at the film surface. Strain as a function of material composition and thickness is considered, as this may play a major role in future nucleation of AlGaN layers. (1) R. J. in a face-to-face configuration, as illustrated in the schematic at left. Kaplar et al 2017, ECS J. Solid State Sci. Technol. 6 Q3061; (2) D. M. Roberts et al 2022, https://arxiv.org/abs/2208.11769; (3) T. Aizawa et al 2008, J Crys Growth 310, 1 22; (4) R. Liu et al 2002, Appl. Phys. Lett. 81, 3182-3184.

ENGINEERING↗

An Organic, Direct Bonded Copper, Multi-Layered, Ultra-Low Inductance Package for High-Power UWBG MOSFETs

The most common metalized substrates used in high-power switching packages consist of a ceramic layer such as Aluminum Nitride (AlN) sandwiched between two copper layers. Ceramic substrates are used because it has the key characteristic of having high dielectric strength while being thermally conductive. A large drawback to ceramic substrates is that they do not allow for a multi-layered circuit design. By replacing the traditional ceramic substrate with organic direct bonded copper (ODBC) we can open a wide range of possibilities when it comes to power module layout such as multi-layered circuits and double-sided cooling. Both benefits are critical while packaging high-performance Gallium Oxide (Ga2O3) MOSFETs. Because of Ga2O3's relatively poor thermal conductivity, a double-sided cooled package becomes necessary. Therefore, the use of ODBC provides the flexibility to fabricate copper traces carrying much higher currents, and by creating a multi-layered package, we can drastically reduce the parasitic inductance inside the power module. Achieving lower parasitic inductance is critical for an ultra-fast Ga2O3 package to avoid excessive voltage overshoot and ringing. Using ODBC, we have designed novel packages capable of handling the challenges presented by fast Ga2O3 switching. Using multi-physics modeling software, we can validate our design before building the prototype. Due to the simple process parameters needed to work with ODBC, we can rapidly create prototypes without using external vendors. This flexibility allows us to quickly design, build, and validate highly complex switching power modules to accommodate next generation, Ga2O3 switching devices.

ADVANCED PROPULSION SYSTEMS,ENGINEERING↗

Domain Nucleation and Growth in an Epitaxially Grown Wurtzite Ferroelectric

Ferroelectric domain nucleation and growth in epitaxial (Al, B, Sc)N films grown on n-GaN substrates are explored using a combination of ferroelectric property measurements and scanning transmission electron microscopy, including novel in situ switching studies. The films are electrically switched to nitrogen-polar (N-polar) and metal-polar (M-polar) configurations, attaining a remanent polarization of 120 µC cm −2 with coercive fields of ≈6 MV cm −1 . In the initial switching cycle, the ferroelectric domains nucleate near the bottom n-GaN electrode and develop domain walls with zigzag morphologies, while residual “dead layers” that do not switch from the as-deposited orientation persist at the top and bottom electrodes. The in situ microscopy experiments reveal that domain walls propagate fastest in the lateral direction, parallel to the electrode/film interface. These findings provide insights into the domain dynamics and structural evolution of wurtzite ferroelectrics, offering implications for next-generation electronic devices.

36 MATERIALS SCIENCE↗

Reduced coercive field in epitaxial thin film of ferroelectric wurtzite Al 0.7 Sc 0.3 N

Epitaxial ferroelectric wurtzite films exhibiting clear polarization-electric field hysteresis behavior are presented. The coercive field of this epitaxial Al 0.7 Sc 0.3 N film on the W/c-sapphire substrate is 0.4±0.3 MV cm -1 (8%) smaller than that of a conventional fiber textured film on a Pt/TiO x /SiO 2 /Si substrate, attributed to the 0.01±0.007 Å smaller c-axis lattice parameter in the epitaxial film. The strain and decrease in the coercive field most likely originate from epitaxial strain rather than the mismatch in the thermal coefficient of expansion. These results provide insight for further coercive field reduction of wurtzite ferroelectrics using epitaxial mismatch strain.

36 MATERIALS SCIENCE↗