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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Characterization of Dislocations in 6H-SiC Wafer Through X-Ray Topography and Ray-Tracing Simulation
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Attack graph-based stochastic modeling approach for enabling cybersecure semiconductor wafer fabrication
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Capillary forces as a limiting factor for sawing of ultrathin silicon wafers by diamond multi-wire saw
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Suppression of crack formation in wafer-scale amorphous SiNx films by residual hydrogen-ligands manipulation
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Crack Catcher AI – Enabling smart fracture mechanics approaches for damage control of thin silicon cells or wafers
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Projected Cost of Gallium Oxide Wafers from Edge-Defined Film-Fed Crystal Growth
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Robust Nanocapacitors Based on Wafer-Scale Single-Crystal Hexagonal Boron Nitride Monolayer Films
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Advancing electrodeionization with conductive ionomer binders that immobilize ion-exchange resin particles into porous wafer substrates
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Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
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Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques
Abstract To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm 2 , which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (R on ). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.
Wafer-scale integration of freestanding photonic devices with color centers in silicon carbide
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Quantitative analysis of dislocations in 4H-SiC wafers using synchrotron X-ray topography with ultra-high angular resolution
Utilization of an Si(331) beam conditioner together with an Si(111) double-crystal monochromator (DCM) enables the angular resolution of synchrotron X-ray topography to be increased by an order of magnitude compared with grazing-incidence topography or back-reflection topography conducted with the DCM alone. This improved technique with extremely small beam divergence is referred to as synchrotron X-ray plane-wave topography (SXPWT). This study demonstrates that the rocking curve width of 4H-SiC 0008 in PWT is only 2.5" and thus the lattice distortion at the scale of 1" will significantly affect the diffracted intensity. This work reports the ultra-high angular resolution in SXPWT which enables detailed probing of the lattice distortion outside the dislocation core in 4H-SiC, where the sign of the Burgers vector can be readily determined through comparison with ray-tracing simulations.
Strategies relating to CMP for die to wafer interconnects utilizing hybrid direct bonding.
Abstract not provided.