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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Wide-Range Temperature Sensors with High-Level Pulse Train Output

Two types of temperature sensors have been developed for wide-range temperature applications. The two sensors measure temperature in the range of -190 to +200 C and utilize a thin-film platinum RTD (resistance temperature detector) as the temperature-sensing element. Other parts used in the fabrication of these sensors include NPO (negative-positive- zero) type ceramic capacitors for timing, thermally-stable film or wirewound resistors, and high-temperature circuit boards and solder. The first type of temperature sensor is a relaxation oscillator circuit using an SOI (silicon-on-insulator) operational amplifier as a comparator. The output is a pulse train with a period that is roughly proportional to the temperature being measured. The voltage level of the pulse train is high-level, for example 10 V. The high-level output makes the sensor less sensitive to noise or electromagnetic interference. The output can be read by a frequency or period meter and then converted into a temperature reading. The second type of temperature sensor is made up of various types of multivibrator circuits using an SOI type 555 timer and the passive components mentioned above. Three configurations have been developed that were based on the technique of charging and discharging a capacitor through a resistive element to create a train of pulses governed by the capacitor-resistor time constant. Both types of sensors, which operated successfully over the wide temperature range, have potential use in extreme temperature environments including jet engines and space exploration missions.

Hammoud, Ahmad↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2010

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗
NASA NTRS2011

Rotation Rate of Saturn's Magnetosphere using CAPS Plasma Measurements

We present the present status of an investigation of the rotation rate of Saturn's magnetosphere using a 3D velocity moment technique being developed at Goddard which is similar to the 2D version used by Sittler et al. for SOI and similar to that used by Thomsen et al.. This technique allows one to nearly cover the full energy range of the Cassini Plasma Spectrometer (CAPS) IMS from 1 V . E/Q < 50 kV. Since our technique maps the observations into a local inertial frame, it does work during roll maneuvers. We make comparisons with the bi-Maxwellian fitting technique developed by Wilson et al. and the similar velocity moment technique by Thomsen et al. . We concentrate our analysis when ion composition data is available, which is used to weight the non-compositional data, referred to as singles data, to separate H+, H2+ and water group ions (W+) from each other. The chosen periods have high enough telemetry rates (4 kbps or higher) so that coincidence ion data, similar to that used by Sittler et al. for SOI is available. The ion data set is especially valuable for measuring flow velocities for protons, which are more difficult to derive using singles data within the inner magnetosphere, where the signal is dominated by heavy ions (i.e., proton peak merges with W+ peak as low energy shoulder). Our technique uses a flux function, which is zero in the proper plasma flow frame, to estimate fluid parameter uncertainties. The comparisons investigate the experimental errors and potential for systematic errors in the analyses, including ours. The rolls provide the best data set when it comes to getting 4PI coverage of the plasma but are more susceptible to time aliasing effects. In the future we will then make comparisons with magnetic field observations, Saturn ionosphere conductivities as presently known and the field aligned currents necessary for the planet to enforce corotation of the rotating plasma.

Sittler, E.↗
NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗
NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗
NASA NTRS2024

The Plasma Proton Environment within Saturn’s F-G Ring Gap as Observed by the Cassini Plasma Spectrometer Ion Mass Spectrometer during Saturn Orbit Insertion

We report on the detection of protons and the potential detection of H 2 + between Saturn's F and G rings based on Cassini Plasma Spectrometer (CAPS) Ion Mass Spectrometer (IMS) time-of-flight (TOF) composition measurements acquired during Saturn Orbit Insertion (SOI) outbound pass. The range in dipole L shell is 2.3 < L < 2.8. Initial results based on TOF data were presented in E. C. Sittler et al., 2017. Here we present the latest results of our analysis. During the SOI outbound pass between the F and G rings the CAPS IMS was in a mode of reduced post-acceleration voltage at -6 kV instead of the usual -14.6 kV. This reduced voltage still allows the analysis of protons since 6 keV protons are minimally scattered by the instrument’s ultrathin carbon foils when compared to heavier ions O + and O 2 + , scattering. Background noise from penetrating radiation and ghost peaks produced by foil-scattered O + ions within the instrument were considered in our analysis. The analysis allowed determination of the proton density, temperature and flow velocity, accounting for spacecraft potential by assuming a convected Maxwellian for the proton velocity distribution function. We find average proton density n P = 3.2 ± 1.1 #/cm 3 , proton temperature T P = 1.74 ± 0.12 eV, proton rotational flow speed V P = 24 ± 1.5 km/s and spacecraft potential  SC = -0.8 ±1.5 V. These results are compared with previous theoretical estimates of H + and H 2 + ions within Saturn’s inner magnetosphere.

E C Sittler↗
DOE OSTI2012

A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

98 NUCLEAR DISARMAMENT, SAFEGUARDS, AND PHYSICAL P↗
DOE OSTI2023

Heterogeneous integration of an electro-optical platform

A hybrid photonic integrated circuit and a method of its manufacture are provided. A SiP functional layer is fabricated on an SOI wafer. A lithium niobate thin film is bonded to the SiP functional layer. The silicon handle layer is removed from the SOI wafer to expose buried oxide, and at least one III-V die is bonded to the exposed buried oxide. In embodiments, at least one waveguiding component is fabricated in the SiP functional layer. In embodiments, the SiP functional layer comprises a top waveguiding layer.

Kodigala, Ashok↗
DOE OSTI2019

Gate Quantum Capacitance Effects in Nanoscale Transistors

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (C Q ). We demonstrate the impact of gate C Q and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. Here, we experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2015

Compact modeling of total ionizing dose and aging effects in MOS technologies

This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The presented approach is suitable for modeling TID and aging effects in advanced MOS devices and ICs.

36 MATERIALS SCIENCE↗
DOE OSTI2013

OM300 Direction Drilling Module

OM300 – Geothermal Direction Drilling Navigation Tool: Design and produce a prototype directional drilling navigation tool capable of high temperature operation in geothermal drilling Accuracies of 0.1° Inclination and Tool Face, 0.5° Azimuth Environmental Ruggedness typical of existing oil/gas drilling Multiple Selectable Sensor Ranges High accuracy for navigation, low bandwidth High G-range & bandwidth for Stick-Slip and Chirp detection Selectable serial data communications Reduce cost of drilling in high temperature Geothermal reservoirs Innovative aspects of project Honeywell MEMS* Vibrating Beam Accelerometers (VBA) APS Flux-gate Magnetometers Honeywell Silicon-On-Insulator (SOI) High-temperature electronics Rugged High-temperature capable package and assembly process

15 GEOTHERMAL ENERGY↗
NASA NTRS2005

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

bolometer↗
DOE OSTI2019

Design and fabrication of ring resonator spectral response through-drop wavelengths selective

In this paper, we discuss the basic characteristics of the SOI based micro-ring resonator, and understand the influence of the high refractive index difference and the small size on the spectral characteristics of the ring resonator. The novelty and importance of the spectral response selectivity of ring resonators is driven by the grating couple technique. This advantage is the periodic variation of the refractive index in the coupled grating, which will result in the coupling of the conduction wave modes. By means of measurement and simulation, observe the changes and trends of the spectrum in steady state and transient state, and finally analyze the performance of the ring resonator in the application of signal processing. It achieves polarization-independent grating couplers with high efficiency, wide bandwidth and low polarization-dependent loss at around the 1560 nm optical communication band. Drop end set laser wavelength correction 1591.9 nm.

36 MATERIALS SCIENCE↗