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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Quantum communications work at SQMS

The Superconducting Quantum Materials and Systems (SQMS) Center is focused on advancing low-loss interconnectivity between quantum processing units (QPUs) to enable scalable quantum computing. In the short term, our goals include the development and optimization of 2D and 3D platforms with remotely entangled modules, refinement in microwave design and control schemes, and the achievement of high-fidelity quantum state transfer between superconducting quantum modules. Looking ahead, we aim to realize modular quantum computing with low-loss interconnects, maximize remote entanglement fidelity and implement robust quantum operations with error correction. We will leverage advanced microwave engineering and material science to optimize the performance of quantum interconnects and the coupling interfaces between the interconnects and the QPUs.

Vallières, André↗
DOE OSTI2024

Material and Interface Engineering Strategies to Mitigate Decoherence in Superconducting Qubits

While significant strides have been made to increase the coherence time of superconducting qubits, further advancements are essential for realizing scalable quantum computing. Decoherence is often a result of loss and noise stemming from two-level systems and excess quasiparticles, arising due to material defects, fabrication processes, and ambient exposure, particularly at surfaces and interfaces. Our recent efforts to mitigate these decoherence mechanisms have employed a variety of strategies, including low-loss surface encapsulation materials, advanced substrate preparation techniques, modifications to metal film growth, and the development of novel fabrication processes. The structural and chemical properties of materials, surfaces, and interfaces are studied using scanning probe microscopy, electron microscopy, photoelectron spectroscopy, mass spectrometry, and X-ray diffraction, which is correlated to device performance metrics, including superconducting resonator internal quality factor and qubit T1 time. This information is used to identify and understand material sources of loss and their origins in the device fabrication process. Through multi-institution efforts within SQMS we have identified the loss mechanism of interstitial hydrogen in niobium-based devices and shown how standard fabrication processes introduce these hydrides, developing strategies to mitigate their formation.1 Furthermore, we have characterized the metal-substrate interface, including the loss of niobium-silicides formed at that interface, and developed silicon surface treatments that reduce atomic scale roughness and oxygen content at the metal-substrate and Josephson junction interfaces.2-4 By developing the connection between materials properties and the overall performance of superconducting quantum circuitry, we can develop fabrication strategies to mitigate material losses, thus supporting the ongoing efforts to enhance coherence time in superconducting quantum devices. 1. Torres-Castanedo, C. G.*, Goronzy, D. P.*, et al., Adv. Funct. Mater., 2401365 (2024) 2. Lu, X., et al., Phys. Rev. Materials 6, 064402 (2022) 3. Berti, G., Appl. Phys. Lett. 122, 192605 (2023) 4. Kopas, C. J., Goronzy, D. P., et al., arXiv:2408.02863 (2024)

Goronzy, Dominic P.↗
DOE OSTI2026

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗
DOE OSTI2026

Sapphire Substrate Trenching to Advance Superconducting High-Coherence Quantum Devices

Achieving longer coherence times in superconducting qubits is essential for advancing quantum information processing and enabling scalable quantum computing. This work presents an innovative fabrication strategy focused on sapphire trenching of the substrate of superconducting high-coherence quantum devices, developed by the SQMS Nanofabrication Taskforce in collaboration with the materials characterization team. In this talk, we present a method to efficiently and consistently trench into the sapphire substrate, without compromising the surface roughness or profile of the etched sapphire. In the literature, trenching in the substrate has been shown to decrease losses, unwanted coupling and thermal stress. Sapphire’s strong covalent bonds make it harder to etch compared to silicon, yet it is more favorable for high-coherence quantum devices due to its lower dielectric losses. This innovative technique opens new possibilities for superconducting qubit fabrication: we fabricated high coherence qubit chips on sapphire substrates with trenching, to demonstrate that it will help pushing towards higher coherence times. By integrating this work with ongoing junction process optimization, design innovation, materials characterization and exploration, we outline a clear pathway toward transmon coherence times reaching millisecond scales and beyond.

Garattoni, S. [Fermilab]↗
DOE OSTI2026

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗
DOE OSTI2026

Sapphire Substrate Trenching to Advance Superconducting High-Coherence Quantum Devices

Achieving longer coherence times in superconducting qubits is essential for advancing quantum information processing and enabling scalable quantum computing. This work presents an innovative fabrication strategy focused on sapphire trenching of the substrate of superconducting high-coherence quantum devices, developed by the SQMS Nanofabrication Taskforce in collaboration with the materials characterization team. In this talk, we present a method to efficiently and consistently trench into the sapphire substrate, without compromising the surface roughness or profile of the etched sapphire. In the literature, trenching in the substrate has been shown to decrease losses, unwanted coupling and thermal stress. Sapphire’s strong covalent bonds make it harder to etch compared to silicon, yet it is more favorable for high-coherence quantum devices due to its lower dielectric losses. This innovative technique opens new possibilities for superconducting qubit fabrication: we fabricated high coherence qubit chips on sapphire substrates with trenching, to demonstrate that it will help pushing towards higher coherence times. By integrating this work with ongoing junction process optimization, design innovation, materials characterization and exploration, we outline a clear pathway toward transmon coherence times reaching millisecond scales and beyond.

Garattoni, S. [Fermilab]↗
DOE OSTI2023

60 Microlensing Events from the Three Years of Zwicky Transient Facility Phase One

Abstract Microlensing events have historically been discovered throughout the Galactic bulge and plane by surveys designed solely for that purpose. We conduct the first multiyear search for microlensing events on the Zwicky Transient Facility (ZTF), an all-sky optical synoptic survey that observes the entire visible northern sky every few nights. We discover 60 high-quality microlensing events in the 3 yr of ZTF-I using the bulk lightcurves in the ZTF Public Data Release 5.19 of our events are found outside of the Galactic plane (∣ b ∣ ≥ 10°), nearly doubling the number of previously discovered events in the stellar halo from surveys pointed toward the Magellanic Clouds and the Andromeda galaxy. We also record 1558 ongoing candidate events as potential microlensing that can continue to be observed by ZTF-II for identification. The scalable and computationally efficient methods developed in this work can be applied to future synoptic surveys, such as the Vera C. Rubin Observatory’s Legacy Survey of Space and Time and the Nancy Grace Roman Space Telescope, as they attempt to find microlensing events in even larger and deeper data sets.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2014

OpenARC: Extensible OpenACC Compiler Framework for Directive-Based Accelerator Programming Study

Directive-based, accelerator programming models such as OpenACC have arisen as an alternative solution to program emerging Scalable Heterogeneous Computing (SHC) platforms. However, the increased complexity in the SHC systems incurs several challenges in terms of portability and productivity. This paper presents an open-sourced OpenACC compiler, called OpenARC, which serves as an extensible research framework to address those issues in the directive-based accelerator programming. This paper explains important design strategies and key compiler transformation techniques needed to implement the reference OpenACC compiler. Moreover, this paper demonstrates the efficacy of OpenARC as a research framework for directive-based programming study, by proposing and implementing OpenACC extensions in the OpenARC framework to 1) support hybrid programming of the unified memory and separate memory and 2) exploit architecture-specific features in an abstract manner. Porting thirteen standard OpenACC programs and three extended OpenACC programs to CUDA GPUs shows that OpenARC performs similarly to a commercial OpenACC compiler, while it serves as a high-level research framework.

Lee, Seyong↗
DOE OSTI2020

High Performance Computing Traffic Simulations for Real-Time Traffic Control of Mobility in Chattanooga Region

In 2019, highway congestion wasted over 3 billion gallons of fuel and caused 8.8 billion hours of lost productivity.1 Research has shown that introducing near-real time traffic controls can significantly reduce congestion. Validated and calibrated traffic simulations enable the modeling of transportation systems and the evaluation of different traffic control actions and schemes given a variety of circumstances that represent likely future scenarios. The developed scenarios can inform the deployment of controls in near real-time to improve freight and passenger vehicle congestion and energy use. In this work, we present simulations used to model the traffic in the Chattanooga, Tennessee, metropolitan area. Simulations were constructed and calibrated using a variety of local, data science enhanced, data sources utilizing open source software including the Simulation of Urban Mobility (SUMO) simulator. High-Performance Computing (HPC) provides a scalable platform with enough computing for the high-fidelity simulation of many scenarios and the application of advance data science especially for large-scale systems. Our simulations include microscopic simulations at a corridor level for traffic signal control, and mesoscopic simulations to evaluate regional operational controls and infrastructure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

System and method for scalable optical interconnect for quantum computing

The present disclosure relates to an interconnect system for interfacing an electronic subsystem to a qubit package, wherein the qubit package has a plurality of independent qubits. The system makes use of an optical fiber cable having a plurality of optical fibers, which is interfaced to the electronic subsystem. A 3D optical structure is used which has a plurality of internal waveguides, and which is configured to interface the optical fiber cable to the qubit package. The 3D optical structure further has at least one subsystem for using the plurality of waveguides to receive signals of a first type from at least one of the qubits package or the optical fiber cable, to convert the signals from the first type to a second type, and to transmit the signals in the second type to the other one of the fiber optic cable or the qubit package.

Patra, Susant K.↗
DOE OSTI2013

Final Scientific Report: A Scalable Development Environment for Peta-Scale Computing

This document is the final scientific report of the project DE-SC000120 (A scalable Development Environment for Peta-Scale Computing). The objective of this project is the extension of the Parallel Tools Platform (PTP) for applying it to peta-scale systems. PTP is an integrated development environment for parallel applications. It comprises code analysis, performance tuning, parallel debugging and system monitoring. The contribution of the Juelich Supercomputing Centre (JSC) aims to provide a scalable solution for system monitoring of supercomputers. This includes the development of a new communication protocol for exchanging status data between the target remote system and the client running PTP. The communication has to work for high latency. PTP needs to be implemented robustly and should hide the complexity of the supercomputer's architecture in order to provide a transparent access to various remote systems via a uniform user interface. This simplifies the porting of applications to different systems, because PTP functions as abstraction layer between parallel application developer and compute resources. The common requirement for all PTP components is that they have to interact with the remote supercomputer. E.g. applications are built remotely and performance tools are attached to job submissions and their output data resides on the remote system. Status data has to be collected by evaluating outputs of the remote job scheduler and the parallel debugger needs to control an application executed on the supercomputer. The challenge is to provide this functionality for peta-scale systems in real-time. The client server architecture of the established monitoring application LLview, developed by the JSC, can be applied to PTP's system monitoring. LLview provides a well-arranged overview of the supercomputer's current status. A set of statistics, a list of running and queued jobs as well as a node display mapping running jobs to their compute resources form the user display of LLview. These monitoring features have to be integrated into the development environment. Besides showing the current status PTP's monitoring also needs to allow for submitting and canceling user jobs. Monitoring peta-scale systems especially deals with presenting the large amount of status data in a useful manner. Users require to select arbitrary levels of detail. The monitoring views have to provide a quick overview of the system state, but also need to allow for zooming into specific parts of the system, into which the user is interested in. At present, the major batch systems running on supercomputers are PBS, TORQUE, ALPS and LoadLeveler, which have to be supported by both the monitoring and the job controlling component. Finally, PTP needs to be designed as generic as possible, so that it can be extended for future batch systems.

97 MATHEMATICS AND COMPUTING↗