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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Parallel Time Integration for Constrained Optimization

The number of transistors in an average processor continues to increase, but individual clock speeds have plateaued. Those transistors are instead going into additional cores, increasing the number of different things that a processor can do at once and placing an emphasis on parallel computation. Many problems in scientific computing follow a time-evolution model, and it can be difficult to solve such problems in parallel across the temporal domain. The Multi-Grid Reduction In Time (MGRIT) algorithm, developed at Lawrence Livermore National Laboratory (LLNL), solves differential equations with a method designed specifically to take advantage of extreme numbers of processors by parallelizing across time. The Tri-diagonal MGRIT (TriMGRIT) algorithm, also developed at LLNL, is a generalization of MGRIT which enables parallel-in-time solving of a greater number of problems. Constrained optimization problems, in particular, may be solved in parallel using TriMGRIT. These consist of choosing a control function such that an objective functional is minimized, constrained by a differential-equation. We consider two such problems: applying torque to a pendulum to bring it to a gentle stop and moving a crowd of people from one distribution into another. We also perform some miscellaneous theoretical and practical research, including investigating the use of a line-search subroutine to refine intermediate TriMGRIT results and preliminary work on strategies for choosing operators for TriMGRIT to use.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

COLLABORATIVE DEVELOPMENT PROJECTS - PHOTONIC MEMORY CONTROLLER MODULE (P-MCM)

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high-performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM).

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

An Integrated Framework for Memory-Centric Analysis: From Trace Collection to Co-Design

The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems—poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing certain behaviors that emerge at larger scales. These limitations reflect a processor-centric design philosophy increasingly misaligned with memory-bound workloads where detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware-assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64\%, confidence-filtered L3 errors of 9.92\%, bandwidth errors of 7.33\%) while providing substantial speedup (26.8×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, prefetching strategies, memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.

Gajaria, Dhruv Mayur↗
DOE OSTI2020

Dynamically adapting mechanism for translation lookaside buffer shootdowns

An operating system (OS) of a processing system having a plurality of processor cores determines a cost associated with different mechanisms for performing a translation lookaside buffer (TLB) shootdown in response to, for example, a virtual address being remapped to a new physical address, and selects a TLB shootdown mechanism to purge outdated or invalid address translations from the TLB based on the determined cost. In some embodiments, the OS selects an inter-processor interrupt (IPI) as the TLB shootdown mechanism if the cost associated with sending an IPI is less than a threshold cost. In some embodiments, the OS compares the cost of using an IPI as the TLB shootdown mechanism versus the cost of sending a hardware broadcast to all processor cores of the processing system as the shootdown mechanism and selects the shootdown mechanism having the lower cost.

42 ENGINEERING↗
DOE OSTI2020

Constructing a conforming Voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is two-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Constructing a conforming voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is three-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗
DOE OSTI2021

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values representing respective voltage magnitudes at voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

Dall'Anese, Emiliano↗
DOE OSTI2021

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony↗
DOE OSTI2021

Bringing OpenCL to Commodity RISC-V CPUs

The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support of the open-source software stack from compiler tools to full-blown operating systems. Parallel computing with today’s Application Programming Interfaces such as OpenCL has proven to be effective at leveraging the parallelism in commodity multi-core processors and programmable parallel accelerators. However, to the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community. Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research. In this work, we extended an Open-source implementation of OpenCL to target RISC-V CPUs. Our work not only cover commodity multi-core RISC-V processors, but also plethora of low- profile embedded RISC-V CPUs that often do not support atomic instructions or multi-threading.

Tine, Blaise↗
DOE OSTI2021

Ultra-compact system for characterization of physical, chemical and ignition properties of fuels

The present disclosure relates to a miniaturized fuel laboratory system that makes use of a housing, a processor housed within the housing, and a fuel inlet port supported from the housing for receiving a quantity of fuel to be used as a fuel test sample. The system may also have at least one fuel sensor housed in the housing in communication with the fuel inlet port for receiving the fuel test sample and carrying out combustion thereof. An electronic component may be housed in the housing, which enables communication with an external remote subsystem. A database may be incorporated which contains at least one of stored fuel characteristics or stored fuel analysis models, accessible by the processor. The processor may use fuel oxidation information generated by the fuel sensor, and at least one of the stored fuel characteristics or stored combustion models, to determine at least one fuel characteristic of the fuel test sample.

McNenly, Matthew J.↗
DOE OSTI2021

Low-observability matrix completion

An example device includes at least one processor configured to receive electrical parameter values corresponding to at least one first location within a power network. The at least one processor is further configured to determine, using matrix completion and based on the at least one electrical parameter value, an estimated value of at least one unknown electrical parameter. The at least one unknown electrical parameter corresponds to a second location within the power network. The at least one processor is also configured to cause at least one device within the power network to modify operation based on the estimated value of the at least one unknown electrical parameter.

Bernstein, Andrey↗
DOE OSTI2021

Vector send operation for message-based communication

Methods and systems for conducting vector send operations are provided. The processor of a sender node receives a request to perform a collective send operation (e.g., MPI_Broadcast) from a user application, requesting a copy of data in one or more send buffers by sent to each of a plurality of destinations in a destination vector. The processor invokes a vector send operation from a software communications library, placing a remote enqueue atomic send command for each destination node of the destination vector in an entry of a transmit data mover (XDM) command queue in a single call. The processor executes all of the commands in the XDM command queue and writes the data in the one or more send buffers into each receive queue of each destination identified in the destination vector.

Byrne, John L.↗
DOE OSTI2022

Control flow guided lock address prefetch and filtering

A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Mashimo, Susumu↗
DOE OSTI2022

Multi-frequency electrical impedance tomography

Apparatus includes a plurality of geological subsurface electrical line sensors spaced apart from each other proximate a predetermined geological subsurface region of interest, with at least one of the electrical line sensors situated as a line source to produce a multi-frequency electrical impedance tomography source signal, and with at least one of the electrical line sensors situated as a line detector to receive the multi-frequency electrical impedance tomography response signal associated with the source signal that propagates through the predetermined geological subsurface region of interest, and a controller including a processor and a memory configured with instructions that, when executed by the processor, cause the processor to determine an electrical mapping over the predetermined geological subsurface region of interest based on the multi-frequency electrical impedance tomography source signal, response signal, and the spatial positions of the geological subsurface electrical line sensors.

Karra, Satish↗
DOE OSTI2022

Phase identification using statistical analysis

A device includes at least one processor configured to determine, based on (i) a first plurality of time-varying electrical measurements corresponding to a feeder head of a power distribution network having a plurality of phases and (ii) a second plurality of time-varying electrical measurements corresponding to a node in the power distribution network, and using statistical analysis, a predicted phase, from the plurality of phases, that corresponds to the node. The processor may be configured to use ranked correlation coefficients (such as the Kendall rank correlation coefficient) to determine the predicted phase and may use principle component analysis. The processor is also configured to cause at least one device of the power distribution network to modify operation based at least on part on the predicted phase.

Veda, Santosh Sambamoorthy↗
DOE OSTI2022

Systems and methods for tensor scheduling

A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

Meister, Benoit J.↗
DOE OSTI2022

In situ data acquisition and real-time analysis system

A testing system for evaluating the performance of an electrical/electronic UUT under dynamic operating conditions. The testing system includes a dynamic testing component (e.g., a centrifuge) for applying a stimulus to the UUT, and an iDAQ system configured to perform in situ data acquisition and real-time data analysis. The iDAQ system may also be subject to the stimulus. The iDAQ system includes a processor (e.g., an SoC) component, a power supply, a CR/I component, an IR component, and a single enclosure. The processor component may control the dynamic testing component, including varying in real-time the stimulus applied to the UUT. The processor component may include multiple input channels, and a high current/voltage subcomponent of the power supply may be configured to supply up to five hundred volts.

Benyhesan, Mohammad K.↗