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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

A sub-cm micromachined electron microscope

A new approach for fabricating macroscopic (approximately 10x10x10 mm(exp 3)) structures with micron accuracy has been developed. This approach combines the precision of semiconductor processing and fiber optic technologies. A (100) silicon wafer is anisotropically etched to create four orthogonal v-grooves and an aperture on each 10x12 mm die. Precision 308 micron optical fibers are sandwiched between the die to align the v-grooves. The fiber is then anodically bonded to the die above and below it. This procedure is repeated to create thick structures and a stack of 5 or 6 die will be used to create a miniature scanning electron microscope (MSEM). Two die in the structure will have a segmented electrode to deflect the beam and correct for astigmatism. The entire structure is UHV compatible. The performance of an SEM improves as its length is reduced and a sub-cm 2 keV MSEM with a field emission source should have approximately 1 nm resolution. A low voltage high resolution MSEM would be useful for the examination of biological specimens and semiconductors with a minimum of damage. The first MSEM will be tested with existing 6 micron thermionic sources. In the future a micromachined field emission source will be used. The stacking technology presented in this paper can produce an array of MSEMs 1 to 30 mm in length with a 1 mm or larger period. A key question being addressed by this research is the optimum size for a low voltage MSEM which will be determined by the required spatial resolution, field of view, and working distance.

Feinerman, A. D.↗
NASA NTRS1977

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗
DOE OSTI2021

Highly Efficient Uniaxial In-Plane Stretching of a 2D Material via Ion Insertion

On-chip dynamic strain engineering requires efficient micro-actuators that can generate large in-plane strains. Inorganic electrochemical actuators are unique in that they are driven by low voltages (≈1 V) and produce considerable strains (≈1%). However, actuation speed and efficiency are limited by mass transport of ions. Minimizing the number of ions required to actuate is thus key to enabling useful “straintronic” devices. Here, it is shown that the electrochemical intercalation of exceptionally few lithium ions into WTe 2 causes large anisotropic in-plane strain: 5% in one in-plane direction and 0.1% in the other. This efficient stretching of the 2D WTe 2 layers contrasts to intercalation-induced strains in related materials which are predominantly in the out-of-plane direction. The unusual actuation of Li x WTe 2 is linked to the formation of a newly discovered crystallographic phase, referred to as Td', with an exotic atomic arrangement. On-chip low-voltage (<0.2 V) control is demonstrated over the transition to the novel phase and its composition. Within the Td'-Li 0.5-δ WTe 2 phase, a uniaxial in-plane strain of 1.4% is achieved with a change of δ of only 0.075. This makes the in-plane chemical expansion coefficient of Td'-Li 0.5-δ WTe 2 far greater than of any other single-phase material, enabling fast and efficient planar electrochemical actuation.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Low Threshold Voltages Electrochemically Drive Gold Migration in Halide Perovskite Devices

The constituent ions of halide perovskite materials are mobile in the solid state and known to participate in reduction/oxidation reactions. Yet few parameters related to electrochemical processes occurring within devices have been carefully determined. Here, we characterize such reactions in model MAPbI3 perovskite devices, and we quantify threshold voltages for key reactions. Gold is oxidized and mobilized under nitrogen, in the dark, at the MAPbI3/Au interface at 0.8 V. When this interface is buffered with the organic hole transport material (HTM), 2,2',7,7'-tetrakis(N,N-di-p-methoxyphenylamino)-9,9'-spirobifluorene, MAPbI3 begins to degrade at 1.2 V; degradation liberates ions that subsequently enable Au migration. Thresholds are insensitive to MAPbI3 thickness or choice of organic HTM or oxide cathode, which suggests that these reactions are driven electrochemically; the electric field across the device is less important. These results have profound implications for understanding in operando degradation pathways of optoelectronic perovskite devices that are varied in terms of interface structures, active material compositions, and ranges of external stressors.

42 ENGINEERING↗
DOE OSTI2020

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10 8 . Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V TH ) and achieve positive V TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. Finally, these results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

A Real-Time Testbed for Smart Inverter Cyber Security Studies

Distributed energy resources (DER) have become a popular solution to modern-day issues surrounding the efficiency and reliability of power generation, as well as climate change concerns. Energy centers are shifting towards incorporating smart inverters with embedded functionalities such as high voltage ride through (HVRT), low voltage ride through (LVRT), active and reactive power compensation. However, the integration of smart inverters leave DER systems highly vulnerable to cybersecurity threats. The distributed network protocol 3 (DNP3) is a common method of communication between grid-tied hardware. Despite its popularity, the level of security leaves all hardware connected to the grid at risk of severe cyber-attacks. Thus, it is important to study any potential cybersecurity threats towards grid-tied smart inverters to mitigate cybersecurity vulnerabilities and refine existing cyber-security protections. This report describes the proposed testbed design to study cybersecurity threats to smart inverters. The testbed utilizes a real-time simulation case in RSCAD that includes a grid-tied wind turbine (WT) topology featuring two back-to-back two-level voltage source converters (BTB,2L-VSCs) and a permanent magnet synchronous machine (PMSM). The simulated case runs within the NovaCor real time digital simulator (RTDS). This report focuses on the design and implementation of a single module of the GTNETx2 card as a distributed network protocol and the configuration of an IEEE 1518 DNP database file that includes input and output variables mapped to different connection points in the grid that transmit and receive discrete, analog, and binary signals on command. This allows realistic emulation of the communication between the smart inverter and the grid for cybersecurity studies.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Low Forward Voltage III-Nitride Red Micro-Light-Emitting Diodes on a Strain Relaxed Template with an InGaN Decomposition Layer

In this study, III-nitride red micro-light-emitting diodes (µLEDs) with ultralow forward voltage are demonstrated on a strain relaxed template. The forward voltage ranges between 2.00 V and 2.05 V at 20 A/cm 2 for device dimensions from 5 x 5 to 100 x 100 µm 2 . The µLEDs emit at 692 nm at 5 A/cm 2 and 637 nm at 100 A/cm 2 , corresponding to a blueshift of 55 nm due to the screening of the internal electric field in the quantum wells. The maximum external quantum efficiency and wall-plug efficiency of µLEDs are 0.31% and 0.21%, respectively. This suggests that efficient III-nitride red µLEDs can be realized with further material optimizations.

36 MATERIALS SCIENCE↗
NASA NTRS1964

Blocking oscillator uses low triggering voltage

To prevent premature triggering of a blocking oscillator, a smaller magnetic core is added to the conventional oscillator circuit. This serves as a second blocking oscillator and has a lower triggering threshold.

Source record↗
NASA NTRS1964

Efficient circuit triggers high-current, high-voltage pulses

Modified circuit uses diodes to effectively disconnect the charging resistors from the circuit during the discharge cycle. Result is an efficient parallel charging, high voltage pulse modulator with low voltage rating of components.

Green, E. D.↗
NASA NTRS2016

Solar Array at Very High Temperatures: Ground Tests

Solar array design for any spacecraft is determined by the orbit parameters. For example, operational voltage for spacecraft in Low Earth Orbit (LEO) is limited by significant differential charging due to interactions with low temperature plasma. In order to avoid arcing in LEO, solar array is designed to generate electrical power at comparatively low voltages (below 100 V) or to operate at higher voltages with encapsulated of all suspected discharge locations. In Geosynchronous Orbit (GEO) differential charging is caused by energetic electrons that produce differential potential between coverglass and conductive spacecraft body in a kilovolt range. In such a case, weakly conductive layer over coverglass (ITO) is one of possible measures to eliminate dangerous discharges on array surface. Temperature variations for solar arrays in both orbits are measured and documented within the range of -150 C +110 C. This wide interval of operational temperatures is regularly reproduced in ground tests with radiative heating and cooling inside shroud with flowing liquid nitrogen. The requirements to solar array design and tests turn out to be more complicated when planned trajectory crosses these two orbits and goes closer to Sun. Conductive layer over coverglass causes sharp increase in parasitic current collected from LEO plasma, high temperature may cause cracks in encapsulating material (RTV), radiative heating of coupon in vacuum chamber becomes practically impossible above 150 C, conductivities of glass and adhesive go up with temperature that decrease array efficiency, and mechanical stresses grow up to critical magnitudes. A few test arrangements and respective results are presented in current paper. Coupons were tested against arcing in simulated LEO and GEO environments under elevated temperatures up to 200 C. The dependence of leakage current on temperature was measured, and electrostatic cleanness was verified for coupons with antireflection (AR) coating over ITO layer.

differential charging↗