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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Bell, L. D.↗
DOE OSTI2015

Tungsten-loaded SMP foam nanocomposites with inherent radiopacity and tunable thermo-mechanical properties

Shape memory polymer (SMP) foams have been developed for use in neurovascular occlusion applications. These materials are predominantly polyurethanes that are known for their biocompatibility and tunable properties. However, these polymers inherently lack X–ray visibility, which is a significant challenge for their use as implantable materials. Herein, low density, highly porous shape memory polyurethane foams were developed with tungsten nanoparticles dispersed into the foam matrix, at increasing concentrations, to serve as a radiopaque agent. Utilizing X–ray fluoroscopy sufficient visibility of the foams at small geometries was observed. Thermal characterization of the foams indicated altered thermal response and delayed foam actuation with increasing nanoparticle loading (because of restricted network mobility). Mechanical testing indicated decreased toughness and strength for higher loading because of disruption of the SMP matrix. Altogether, filler addition imparted x–ray visibility to the SMP foams and allowed for tuned control of the transition temperature and actuation kinetics for the material.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Sage: parallel semi-asymmtric graph algorithms for NVRAMs

Non-volatile main memory (NVRAM) technologies provide an attractive set of features for large-scale graph analytics, including byte-addressability, low idle power, and improved memory-density. NVRAM systems today have an order of magnitude more NVRAM than traditional memory (DRAM). NVRAM systems could therefore potentially allow very large graph problems to be solved on a single machine, at a modest cost. However, a significant challenge in achieving high performance is in accounting for the fact that NVRAM writes can be much more expensive than NVRAM reads. In this paper, we propose an approach to parallel graph analytics using the Parallel Semi-Asymmetric Model (PSAM), in which the graph is stored as a read-only data structure (in NVRAM), and the amount of mutable memory is kept proportional to the number of vertices. Similar to the popular semi-external and semi-streaming models for graph analytics, the PSAM approach assumes that the vertices of the graph fit in a fast read-write memory (DRAM), but the edges do not. In NVRAM systems, our approach eliminates writes to the NVRAM, among other benefits. To experimentally study this new setting, we develop Sage, a parallel semi-asymmetric graph engine with which we implement provably-efficient (and often work-optimal) PSAM algorithms for over a dozen fundamental graph problems. We experimentally study Sage using a 48--core machine on the largest publicly-available real-world graph (the Hyperlink Web graph with over 3.5 billion vertices and 128 billion edges) equipped with Optane DC Persistent Memory, and show that Sage outperforms the fastest prior systems designed for NVRAM. Importantly, we also show that Sage nearly matches the fastest prior systems running solely in DRAM, by effectively hiding the costs of repeatedly accessing NVRAM versus DRAM.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2000

Quantitative analysis of charge injection and discharging of Si nanocrystals and arrays by electrostatic force microscopy

NASA requirements for computing and memory for microspacecraft emphasizes high density, low power, small size, and radiation hardness. The distributed nature of a storage elements in nanocrystal floating-gate memories leads to instrinsic fault tolerance and radiation-hardness. Nanocrystal-based memories also offer the possibility of a faster, lower power operation.

atomic↗
DOE OSTI2018

Breaking the Current‐Retention Dilemma in Cation‐Based Resistive Switching Devices Utilizing Graphene with Controlled Defects

Abstract Cation‐based resistive switching (RS) devices, dominated by conductive filaments (CF) formation/dissolution, are widely considered for the ultrahigh density nonvolatile memory application. However, the current‐retention dilemma that the CF stability deteriorates greatly with decreasing compliance current makes it hard to decrease operating current for memory application and increase driving current for selector application. By centralizing/decentralizing the CF distribution, this current‐retention dilemma of cation‐based RS devices is broken for the first time. Utilizing the graphene impermeability, the cation injecting path to the RS layer can be well modulated by structure‐defective graphene, leading to control of the CF quantity and size. By graphene defect engineering, a low operating current (≈1 µA) memory and a high driving current (≈1 mA) selector are successfully realized in the same material system. Based on systematically materials analysis, the diameter of CF, modulated by graphene defect size, is the major factor for CF stability. Breakthrough in addressing the current‐retention dilemma will instruct the future implementation of high‐density 3D integration of RS memory immune to crosstalk issues.

Zhao, Xiaolong↗
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
NASA NTRS1971

Annealing effects in plated-wire memory elements. I - Interdiffusion of copper and Permalloy.

Results of investigations using X-ray diffraction and electron-beam microprobe techniques have shown that copper and Permalloy platings interdiffuse at low temperatures when plated-wire memory elements are annealed for times as short as 50 hr. Measurable interdiffusion between Permalloy platings and gold substrates does not occur in similar conditions. Both magnetic and compositional changes during aging are found to occur by a thermally activated process with activation energies around 38 kcal/mol. It is shown, however, that copper-diffusion and magnetic-dispersion changes during aging are merely concurrent processes, neither being the other's cause.

Knudson, C. I.↗
DOE OSTI2015

Optically controlled multiple switching operations of DNA biopolymer devices

We present optically tunable operations of deoxyribonucleic acid (DNA) biopolymer devices, where a single high-resistance state, write-once read-many-times memory state, write-read-erase memory state, and single low-resistance state can be achieved by controlling UV irradiation time. The device is a simple sandwich structure with a spin-coated DNA biopolymer layer sandwiched by two electrodes. Upon irradiation, the electrical properties of the device are adjusted owing to a phototriggered synthesis of silver nanoparticles in DNA biopolymer, giving rise to multiple switching scenarios. This technique, distinct from the strategy of doping of pre-formed nanoparticles, enables a post-film fabrication process for achieving optically controlled memory device operations, which provides a more versatile platform to fabricate organic memory and optoelectronic devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Checksumming strategies for data in volatile memories

The increase in the number of processors needed to build exascale systems implies that the mean time between failure will further decrease, making it increasingly important to develop scalable techniques for fault tolerance. In this paper we develop an efficient checksum-based approach to fault tolerance for data in volatile memory systems, i.e., an approach without the need to save any data on stable persistent storage. The developed scheme is applicable in multiple scenarios, including: 1) online recovery of large read-only data structures from the memory of failed nodes, with very low storage overhead 2) online recovery from soft errors in blocked data, and 3) online recovery of read/write data via in-memory check-pointing. The approach uses a logical multi-dimension view of the data to be protected. Changing the dimensionality of the data view enables a trade-off between multiple factors, including the storage overheads, the checksum generation time, the failure recovery time, and the number of faults that can be tolerated. Experimental results demonstrating effectiveness are presented on a Cray XE6 system.

Arafat, Md H.↗
NASA NTRS1984

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

Costello, D. J., Jr.↗
NASA NTRS2002

Advanced Engine Cycles Analyzed for Turbofans With Variable-Area Fan Nozzles Actuated by a Shape Memory Alloy

Advanced, large commercial turbofan engines using low-fan-pressure-ratio, very high bypass ratio thermodynamic cycles can offer significant fuel savings over engines currently in operation. Several technological challenges must be addressed, however, before these engines can be designed. To name a few, the high-diameter fans associated with these engines pose a significant packaging and aircraft installation challenge, and a large, heavy gearbox is often necessary to address the differences in ideal operating speeds between the fan and the low-pressure turbine. Also, the large nacelles contribute aerodynamic drag penalties and require long, heavy landing gear when mounted on conventional, low wing aircraft. Nevertheless, the reduced fuel consumption rates of these engines are a compelling economic incentive, and fans designed with low pressure ratios and low tip speeds offer attractive noise-reduction benefits. Another complication associated with low-pressure-ratio fans is their need for variable flow-path geometry. As the design fan pressure ratio is reduced below about 1.4, an operational disparity is set up in the fan between high and low flight speeds. In other words, between takeoff and cruise there is too large a swing in several key fan parameters-- such as speed, flow, and pressure--for a fan to accommodate. One solution to this problem is to make use of a variable-area fan nozzle (VAFN). However, conventional, hydraulically actuated variable nozzles have weight, cost, maintenance, and reliability issues that discourage their use with low-fan-pressure-ratio engine cycles. United Technologies Research, in cooperation with NASA, is developing a revolutionary, lightweight, and reliable shape memory alloy actuator system that can change the on-demand nozzle exit area by up to 20 percent. This "smart material" actuation technology, being studied under NASA's Ultra-Efficient Engine Technology (UEET) Program and Revolutionary Concepts in Aeronautics (RevCon) Program, has the potential to enable the next generation of efficient, quiet, very high bypass ratio turbofans. NASA Glenn Research Center's Propulsion Systems Analysis Office, along with NASA Langley Research Center's Systems Analysis Branch, conducted an independent analytical assessment of this new technology to provide strategic guidance to UEET and RevCon. A 2010-technology-level high-spool engine core was designed for this evaluation. Two families of low-spool components, one with and one without VAFN's, were designed to operate with the core. This "constant core" approach was used to hold most design parameters constant so that any performance differences between the VAFN and fixed nozzle cycles could be attributed to the VAFN technology alone. In this manner, the cycle design regimes that offer a performance payoff when VAFN's are used could be identified. The NASA analytical model of a performance-optimized VAFN turbofan with a fan pressure ratio of 1.28 is shown. Mission analyses of the engines were conducted using the notional, long-haul, advanced commercial twinjet shown. A high wing design was used to accommodate the large high-bypassratio engines. The mission fuel reduction benefit of very high bypass shape-memory-alloy VAFN aircraft was calculated to be 8.3 percent lower than a moderate bypass cycle using a conventional fixed nozzle. Shape-memory-alloy VAFN technology is currently under development in NASA's UEET and RevCon Programs.

Berton, Jeffrey J.↗
DOE OSTI2024

A GPU accelerated mixed-precision Smoothed Particle Hydrodynamics framework with cell-based relative coordinates

Smoothed Particle Hydrodynamics (SPH) is essential for modeling complex large-deformation problems across various applications, requiring significant computational power. A major portion of SPH computation time is dedicated to the Nearest Neighboring Particle Search (NNPS) process. While advanced NNPS algorithms have been developed to enhance SPH efficiency, the potential efficiency gains from modern computation hardware remain underexplored. Here, this study investigates the impact of GPU parallel architecture, low-precision computing on GPUs, and GPU memory management on NNPS efficiency. Our approach employs a GPU-accelerated mixed-precision SPH framework, utilizing low precision float-point 16 (FP16) for NNPS while maintaining high precision for other components. To ensure FP16 accuracy in NNPS, we introduce a Relative Coordinated-based Link List (RCLL) algorithm, storing FP16 relative coordinates of particles within background cells. Our testing results show three significant speedup rounds for CPU-based NNPS algorithms. The first comes from parallel GPU computations, with up to a 1000x efficiency gain. The second is achieved through low-precision GPU computing, where the proposed FP16-based RCLL algorithm offers a 1.5x efficiency improvement over the FP64-based approach on GPUs. By optimizing GPU memory bandwidth utilization, the efficiency of the FP16 RCLL algorithm can be further boosted by 2.7x, as demonstrated in an example with 1 million particles. Our code is released at https://github.com/pnnl/lpNNPS4SPH.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Enhanced memory effect with embedded graphene nanoplatelets in ZnO charge trapping layer

A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) is demonstrated. The memory shows a large threshold voltage V{sub t} shift (4 V) at low operating voltage (6/−6 V), good retention (>10 yr), and good endurance characteristic (>10{sup 4} cycles). This memory performance is compared to control devices with graphene nanoplatelets (or ZnO) and a thicker tunnel oxide. These structures showed a reduced V{sub t} shift and retention characteristic. The GNIZ structure allows for scaling down the tunnel oxide thickness along with improving the memory window and retention of data. The larger V{sub t} shift indicates that the ZnO adds available trap states and enhances the emission and retention of charges. The charge emission mechanism in the memory structures with graphene nanoplatelets at an electric field E ≥ 5.57 MV/cm is found to be based on Fowler-Nordheim tunneling. The fabrication of this memory device is compatible with current semiconductor processing, therefore, has great potential in low-cost nano-memory applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer

In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al{sub 2}O{sub 3} layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-V{sub gate} measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (V{sub t}) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the V{sub t} shift direction indicates that electrons tunnel from channel to charge storage layer.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

A study on fast digital discrimination of neutron and gamma-ray for improvement neutron emission profile measurement

Neutron and γ-ray (n-γ) discrimination with a digital signal processing system has been used to measure the neutron emission profile in magnetic confinement fusion devices. However, a sampling rate must be set low to extend the measurement time because the memory storage is limited. Time jitter decreases a discrimination quality due to a low sampling rate. As described in this paper, a new charge comparison method was developed. Furthermore, automatic n-γ discrimination method was examined using a probabilistic approach. Analysis results were investigated using the figure of merit. Results show that the discrimination quality was improved. Automatic discrimination was applied using the EM algorithm and k-means algorithm.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2019

Distributed-memory lattice H-matrix factorization

We parallelize the LU factorization of a hierarchical low-rank matrix (H-matrix) on a distributed-memory computer. This is much more difficult than the H-matrix-vector multiplication due to the dataflow of the factorization, and it is much harder than the parallelization of a dense matrix factorization due to the irregular hierarchical block structure of the matrix. Block low-rank (BLR) format gets rid of the hierarchy and simplifies the parallelization, often increasing concurrency. However, this comes at a price of losing the near-linear complexity of the H-matrix factorization. In this work, we propose to factorize the matrix using a “lattice H-matrix” format that generalizes the BLR format by storing each of the blocks (both diagonals and off-diagonals) in the H-matrix format. These blocks stored in the H-matrix format are referred to as lattices. Thus, this lattice format aims to combine the parallel scalability of BLR factorization with the near-linear complexity of H-matrix factorization. We first compare factorization performances using the H-matrix, BLR, and lattice H-matrix formats under various conditions on a shared-memory computer. Our performance results show that the lattice format has storage and computational complexities similar to those of the H-matrix format, and hence a much lower cost of factorization than BLR. In conclusion, we then compare the BLR and lattice H-matrix factorization on distributed-memory computers. Our performance results demonstrate that compared with BLR, the lattice format with the lower cost of factorization may lead to faster factorization on the distributed-memory computer.

97 MATHEMATICS AND COMPUTING↗