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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Detailed Studies of Pixelated CZT Detectors Grown with the Modified Horizontal Bridgman Method

The detector material Cadmium Zinc Telluride (CZT) achieves excellent spatial resolution and good energy resolution over a broad energy range, several keV up to some MeV. Presently, there are two main methods to grow CZT crystals, the Modified High-Pressure Bridgman (MHB) and the High-Pressure Bridgman (HPB) process. The study presented in this paper is based on MHB CZT substrates from the company Orbotech Medical Solutions Ltd. [Orbotech Medical Solutions Ltd., 10 Plaut St., Park Rabin, P.O. Box 2489, Rehovot, Israel, 76124]. Former studies have shown that high-work-function materials on the cathode side reduce the leakage current and, therefore, improve the energy resolution at lower energies. None of the studies have emphasized on the anode contact material. Therefore, we present in this paper the result of a detailed study in which for the first time the cathode material was kept constant and the anode material was varied. We used four different anode materials: Indium, Titanium, Chromium and Gold, metals with work-functions between 4.1 eV and 5.1 eV. The detector size was 2.0 x 2.0 x 0.5 cu cm with 8 x 8 pixels and a pitch of 2.46 mm. The best performance was achieved with the low-work-function materials Indium and Titanium with energy resolutions of 2.0 keV (at 59 keV) and 1.9 keV (at 122 keV) for Titanium and 2.1 keV (at 59 keV) and 2.9 keV (at 122 keV) for Indium. Taking into account the large pixel pitch of 2.46 mm, these resolutions are very competitive in comparison to those achieved with detectors made of material produced with the more expensive conventional HPB method. We present a detailed comparison of our detector response with 3D simulations. The latter comparisons allow us to determine the mobility-lifetime-products (mu tau-products) for electrons and holes. Finally, we evaluated the temperature dependency of the detector performance and ls-products. For many applications temperature dependence is important, therefore, we extended the scope of our study to temperatures as low as -30 C. There are two important results. The breakdown voltage increases with decreasing temperature, and electron mobility-lifetime-product decreases by about 30% over a range from 20 C to -30 C. The latter effect causes the energy resolution to deteriorate, but the concomitantly increasing breakdown voltage makes it possible to increase the applied bias voltage and restore the full performance

Jung, I.↗
NASA NTRS2011

Reliability Evaluation of Base-Metal-Electrode Multilayer Ceramic Capacitors for Potential Space Applications

Base-metal-electrode (BME) ceramic capacitors are being investigated for possible use in high-reliability spacelevel applications. This paper focuses on how BME capacitors construction and microstructure affects their lifetime and reliability. Examination of the construction and microstructure of commercial off-the-shelf (COTS) BME capacitors reveals great variance in dielectric layer thickness, even among BME capacitors with the same rated voltage. Compared to PME (precious-metal-electrode) capacitors, BME capacitors exhibit a denser and more uniform microstructure, with an average grain size between 0.3 and 0.5 m, which is much less than that of most PME capacitors. BME capacitors can be fabricated with more internal electrode layers and thinner dielectric layers than PME capacitors because they have a fine-grained microstructure and do not shrink much during ceramic sintering. This makes it possible for BME capacitors to achieve a very high capacitance volumetric efficiency. The reliability of BME and PME capacitors was investigated using highly accelerated life testing (HALT). Most BME capacitors were found to fail with an early avalanche breakdown, followed by a regular dielectric wearout failure during the HALT test. When most of the early failures, characterized with avalanche breakdown, were removed, BME capacitors exhibited a minimum mean time-to-failure (MTTF) of more than 105 years at room temperature and rated voltage. Dielectric thickness was found to be a critical parameter for the reliability of BME capacitors. The number of stacked grains in a dielectric layer appears to play a significant role in determining BME capacitor reliability. Although dielectric layer thickness varies for a given rated voltage in BME capacitors, the number of stacked grains is relatively consistent, typically around 12 for a number of BME capacitors with a rated voltage of 25V. This may suggest that the number of grains per dielectric layer is more critical than the thickness itself for determining the rated voltage and the life expectancy of the BME capacitor. The leakage current characterization and the failure analysis results suggest that most of these early avalanche failures are due to the extrinsic minor construction defects introduced during fabrication of BME capacitors. The concentration of the extrinsic defects must be reduced if the BME capacitors are considered for high reliability applications. There are two approaches that can reduce or prevent the occurrence of early failure in BME capacitors: (1) to reduce the defect concentration with improved processing control; (2) to prevent the use of BME capacitors under harsh external stress levels so that the extrinsic defects will never be triggered for a failure. In order to do so appropriate dielectric layer thickness must be determined for a given rated voltage.

Liu, David (Donhang)↗
NASA NTRS2005

Making AlN(x) Tunnel Barriers Using a Low-Energy Nitrogen-Ion Beam

A technique based on accelerating positive nitrogen ions onto an aluminum layer has been demonstrated to be effective in forming thin (<2 nm thick) layers of aluminum nitride (AlN(x)) for use as tunnel barriers in Nb/Al-AlN(x)/Nb superconductor/insulator/ superconductor (SIS) Josephson junctions. AlN(x) is the present material of choice for tunnel barriers because, to a degree greater than that of any other suitable material, it offers the required combination of low leakage current at high current density and greater thermal stability. While ultra-thin AlN films with good thickness and stoichiometry control are easily formed using techniques such as reactive molecular beam epitaxy and chemical vapor deposition, growth temperatures of 900 C are necessary for the dissociative adsorption of nitrogen from either nitrogen (N2) or ammonia (NH3). These growth temperatures are prohibitively high for the formation of tunnel barriers on Nb films because interfacial reactions at temperatures as low as 200 to 300 C degrade device properties. Heretofore, deposition by reactive sputtering and nitridation of thin Al layers with DC and RF nitrogen plasmas have been successfully used to form AlN barriers in SIS junctions. However, precise control over critical current density Jc has proven to be a challenge, as is attaining adequate process reproducibility from system to system. The present ion-beam technique is an alternative to the plasma or reactive sputtering techniques as it provides a highly controlled arrival of reactive species, independent of the electrical conditions of the substrate or vacuum chamber. Independent and accurate control of parameters such as ion energy, flux, species, and direction promises more precise control of film characteristics such as stoichiometry and thickness than is the case with typical plasma processes. In particular, the background pressure during ion-beam nitride growth is 2 or 3 orders of magnitude lower, minimizing the formation of compounds with contaminants, which is critical in devices the performance of which is dictated by interfacial characteristics. In addition, the flux of incoming species can be measured in situ using ion probes so that the dose can be controlled accurately. The apparatus used in the present ion-beam technique includes a vacuum chamber containing a commercial collimated- ion-beam source, a supply of nitrogen and argon, and an ion probe for measuring the ion dose. Either argon or nitrogen can be used as the feed gases for the ion source, depending on whether cleaning of the substrate or growth of the nitride, respectively, is desired. Once the Nb base electrode and Al proximity layer have been deposited, the N2 gas line to the ion beam is vented and purged, and the ion-source is turned on until a stable discharge is obtained. The substrate is moved over the ion-beam source to expose the Al surface layer to the ion beam (see figure) for a specified duration for the formation of the nitride tunnel barrier. Next, the Nb counter-electrode layer is deposited on the nitride surface layer. The Nb/Al- AlN(x)/Nb-trilayer-covered substrate is then patterned into individual devices by use of conventional integrated-circuit processing techniques.

Kaul, Anupama↗
NASA NTRS2012

Some Aspects of the Failure Mechanisms in BaTiO3-Based Multilayer Ceramic Capacitors

The objective of this presentation is to gain insight into possible failure mechanisms in BaTiO3-based ceramic capacitors that may be associated with the reliability degradation that accompanies a reduction in dielectric thickness, as reported by Intel Corporation in 2010. The volumetric efficiency (microF/cm3) of a multilayer ceramic capacitor (MLCC) has been shown to not increase limitlessly due to the grain size effect on the dielectric constant of ferroelectric ceramic BaTiO3 material. The reliability of an MLCC has been discussed with respect to its structure. The MLCCs with higher numbers of dielectric layers will pose more challenges for the reliability of dielectric material, which is the case for most base-metal-electrode (BME) capacitors. A number of MLCCs manufactured using both precious-metal-electrode (PME) and BME technology, with 25 V rating and various chip sizes and capacitances, were tested at accelerated stress levels. Most of these MLCCs had a failure behavior with two mixed failure modes: the well-known rapid dielectric wearout, and so-called 'early failures." The two failure modes can be distinguished when the testing data were presented and normalized at use-level using a 2-parameter Weibull plot. The early failures had a slope parameter of Beta >1, indicating that the early failures are not infant mortalities. Early failures are triggered due to external electrical overstress and become dominant as dielectric layer thickness decreases, accompanied by a dramatic reduction in reliability. This indicates that early failures are the main cause of the reliability degradation in MLCCs as dielectric layer thickness decreases. All of the early failures are characterized by an avalanche-like breakdown leakage current. The failures have been attributed to the extrinsic minor construction defects introduced during fabrication of the capacitors. A reliability model including dielectric thickness and extrinsic defect feature size is proposed in this presentation. The model can be used to explain the Intel-reported reliability degradation in MLCCs with respect to the reduction of dielectric thickness. It can also be used to estimate the reliability of a MLCC based on its construction and microstructure parameters such as dielectric thickness, average grain size, and number of dielectric layers. Measures for preventing early failures are also discussed in this document.

Liu, David Donhang↗
NASA NTRS2013

What Reliability Engineers Should Know about Space Radiation Effects

Space radiation in space systems present unique failure modes and considerations for reliability engineers. Radiation effects is not a one size fits all field. Threat conditions that must be addressed for a given mission depend on the mission orbital profile, the technologies of parts used in critical functions and on application considerations, such as supply voltages, temperature, duty cycle, and redundancy. In general, the threats that must be addressed are of two types-the cumulative degradation mechanisms of total ionizing dose (TID) and displacement damage (DD). and the prompt responses of components to ionizing particles (protons and heavy ions) falling under the heading of single-event effects. Generally degradation mechanisms behave like wear-out mechanisms on any active components in a system: Total Ionizing Dose (TID) and Displacement Damage: (1) TID affects all active devices over time. Devices can fail either because of parametric shifts that prevent the device from fulfilling its application or due to device failures where the device stops functioning altogether. Since this failure mode varies from part to part and lot to lot, lot qualification testing with sufficient statistics is vital. Displacement damage failures are caused by the displacement of semiconductor atoms from their lattice positions. As with TID, failures can be either parametric or catastrophic, although parametric degradation is more common for displacement damage. Lot testing is critical not just to assure proper device fi.mctionality throughout the mission. It can also suggest remediation strategies when a device fails. This paper will look at these effects on a variety of devices in a variety of applications. This paper will look at these effects on a variety of devices in a variety of applications. (2) On the NEAR mission a functional failure was traced to a PIN diode failure caused by TID induced high leakage currents. NEAR was able to recover from the failure by reversing the current of a nearby Thermal Electric Cooler (turning the TEC into a heater). The elevated temperature caused the PIN diode to anneal and the device to recover. It was by lot qualification testing that NEAR knew the diode would recover when annealed. This paper will look at these effects on a variety of devices in a variety of applications. Single Event Effects (SEE): (1) In contrast to TID and displacement damage, Single Event Effects (SEE) resemble random failures. SEE modes can range from changes in device logic (single-event upset, or SEU). temporary disturbances (single-event transient) to catastrophic effects such as the destructive SEE modes, single-event latchup (SEL). single-event gate rupture (SEGR) and single-event burnout (SEB) (2) The consequences of nondestructive SEE modes such as SEU and SET depend critically on their application--and may range from trivial nuisance errors to catastrophic loss of mission. It is critical not just to ensure that potentially susceptible devices are well characterized for their susceptibility, but also to work with design engineers to understand the implications of each error mode. -For destructive SEE, the predominant risk mitigation strategy is to avoid susceptible parts, or if that is not possible. to avoid conditions under which the part may be susceptible. Destructive SEE mechanisms are often not well understood, and testing is slow and expensive, making rate prediction very challenging. (3) Because the consequences of radiation failure and degradation modes depend so critically on the application as well as the component technology, it is essential that radiation, component. design and system engineers work togetherpreferably starting early in the program to ensure critical applications are addressed in time to optimize the probability of mission success.

DiBari, Rebecca↗
NASA NTRS2011

Superlattice Barrier Infrared Detector Development at the Jet Propulsion Laboratory

We report recent efforts in achieving state-of-the-art performance in type-II superlattice based infrared photodetectors using the barrier infrared detector architecture. We used photoluminescence measurements for evaluating detector material and studied the influence of the material quality on the intensity of the photoluminescence. We performed direct noise measurements of the superlattice detectors and demonstrated that while intrinsic 1/f noise is absent in superlattice heterodiode, side-wall leakage current can become a source of strong frequency-dependent noise. We developed an effective dry etching process for these complex antimonide-based superlattices that enabled us to fabricate single pixel devices as well as large format focal plane arrays. We describe the demonstration of a 1024x1024 pixel long-wavelength infrared focal plane array based the complementary barrier infrared detector (CBIRD) design. An 11.5 micron cutoff focal plane without anti-reflection coating has yielded noise equivalent differential temperature of 53 mK at operating temperature of 80 K, with 300 K background and cold-stop. Imaging results from a recent 10 ?m cutoff focal plane array are also presented.

superlattice↗
NASA NTRS2010

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗
NASA NTRS2014

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

Time dependence of absorption voltages (V(sub abs)) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on V(sub abs)), cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on V(sub abs)), are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks.

ceramic capacitor↗
NASA NTRS2016

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

Time dependence of absorption voltages (Vabs) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on Vabs, cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on Vabs, are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks. Index Terms: Ceramic capacitor, insulation resistance, dielectric absorption, cracking.

cracking↗
NASA NTRS2017

Degradation and ESR Failures in MnO2 Chip Tantalum Capacitors

Equivalent series resistance (ESR) of chip tantalum capacitors determines the rate of energy delivery and power dissipation thus affecting temperature and reliability of the parts. Employment of advanced capacitors with reduced ESR decreases power losses and improves efficiency in power systems. Stability of ESR is essential for correct operations of power units and might cause malfunctioning and failures when ESR becomes too high or too low. Several cases with ESR values in CWR29 capacitors exceeding the specified limit that were observed recently raised concerns regarding environmental factors affecting ESR and the adequacy of the existing screening and qualification testing. In this work, results of stress testing of various types of military and commercial capacitors obtained over years by GSFC test lab and NEPP projects that involved ESR measurements are described. Environmental stress tests include testing in humidity and vacuum chambers, temperature cycling, long-term storage at high temperatures, and various soldering simulation tests. Note that in many cases parts failed due to excessive leakage currents or reduced breakdown voltages. However, only ESR-related degradation and failures are discussed. Mechanisms of moisture effect are discussed and recommendations to improve screening and qualification system are suggested.

Equivalent Series Resistance (ESR)↗
NASA NTRS2017

Micron MT29F128G08AJAAA 128GB Asynchronous Flash Memory Total Ionizing Dose Characterization Test Report

The purpose of this test was to characterize the Micron MT29F128G08AJAAAs parameter degradation for total dose response and to evaluate and compare lot date codes for sensitivity. In the test, the device was exposed to both low dose and high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits and overall chip and die health were investigated to determine which lot is more robust.

Flash Memory↗
NASA NTRS2017

Packaging Technology for Dielectric-Coating-Less Heavy Ion Radiation Testing of High-Voltage (HV) Electronic Parts

Testing high voltage (HV) electronic parts (greater than 300 V) for sudden event effects (SEE) caused by cosmic rays in the space environment, consisting of energetic heavy-ions, and neutron radiation in the upper atmosphere is a crucial step towards using these parts in spacecraft and aircraft. Due to the nature of cosmic radiation and neutrons, electronic parts are tested for SEE without any packaging and/or shielding over the top of the device. In the case of commercial HV parts, the top of the packaging is etched off and then a thin dielectric coating is placed over the part in order to avoid electrical arcing between the device surface and wire bonds and other components. Even though the effects of the thin dielectric layer on SEE testing can be accounted for, the dielectric layer significantly hinders post testing failure analysis. Replicating the test capability of state-of-the-art packaging while eliminating the need for post radiation test processing of the die surface (that obscures failure analysis) is the goal. To that end, a new packaging concept for HV parts has been developed that requires no dielectric coating over the part. Testing of prototype packages used with Schottky diodes (rated at 1200V) has shown no electrical arcing during testing and leakage currents during reverse bias testing are within the manufactures specifications.

High Voltage↗
NASA NTRS2018

Solid State Ephemeral Electric Potential and Electric Field Sensor

Systems, methods, and devices of the various embodiments provide a field effect transistor (FET) that controls equilibrium by reversing the effects of leakage currents affecting the gate response of the FET by using an equilibrium pump electrode. The equilibrium reversing gate FETs (ergFETs) of the various embodiments, may include an equilibrium pump electrode located within a non-conducting gap. The ergFETs of the various embodiments may provide solid state ephemeral electric potential and electric field sensor systems and methods for measuring ephemeral electric potentials and electric fields.

Generazio, Edward R.↗
NASA NTRS2019

ISSI IS46DR16640B-25DBA25 DDR2 SDRAM Total Ionizing Dose Characterization Test Report

The purpose of this testing is to characterize the ISSI IS46DR16640B-25DBA25 parameter degradation for total dose response. This test’s purpose is to evaluate and compare lot date codes for sensitivity. In the test, the device is exposed to both low dose and high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits or addresses, and overall chip and die health are investigated to determine which lot is more robust. These parameters directly affect the functionality of the memory within a system and may determine thresholds necessary to mitigate failure.

Total Ionizing Dose (TID)↗
NASA NTRS2017

Reliability Issues with PME and BME Ceramic Capacitors

Exposure of chip MnO2 tantalum capacitors to humid environments might result in increased ESR, leakage currents, and first turn-on failures. However, there is a lack of literature data on the effect of moisture on reverse bias behavior of the parts. The presence of moisture can also result in pop-corning when a high water vapor pressure develops when moisture absorbed in pores of tantalum slugs vaporizes instantly during soldering process resulting in damage to capacitors. A study of kinetics of moisture ingress to and release from active elements of capacitors would allow a better understanding of degradation mechanisms and is important for preventing failures. In this work, a technique for investigation of moisture sorption and desorption in solid chip tantalum capacitors that employs tantalum slugs as a humidity sensor have been developed and kinetics of the process analyzed for different types of capacitors at temperatures from room to 125 C. A model that relates diffusion characteristics of polymer cases and size of the slugs to characteristic times of moisture sorption has been developed. A strong effect of moisture on long-term degradation of reverse bias currents in MnO2 cathode capacitors has been demonstrated and physical mechanisms discussed.

degradation↗
NASA NTRS2019

Effect of Environments on Parametric Degradation in Polymer Tantalum Capacitors

Chip polymer tantalum capacitors (CPTCs) are more sensitive to environments compared to conventional, MnO2 cathode capacitors. Contrary to MnO2 capacitors, CPTCs can degrade with time of storage even in dry conditions, that might limit their use for space applications. Performance of CPTCs depends on the amount of moisture in the slug, and varies with time of storage after manufacturing. For this reason, characteristics of the parts and qualification testing should be carried out after preconditioning to stabilize moisture content. This work analyzes kinetics of moisture sorption and desorption in different types of CPTCs from three manufacturers. Variations of capacitance, dissipation factor, ESR, and leakage currents caused by exposure to humid, dry, and radiation environments are discussed. Examples of the effects of long-term exposure to vacuum and humid environments at 85%RH are presented. Temperature dependencies of the characteristic times of moisture diffusion allow for assessments of the bake-out times that are necessary to avoid pop-corning failures after soldering and to precondition parts before qualification testing.

Teverovsky, Alexander↗