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NASA NTRS1995

Hydrogen passivation of n+p and p+n heteroepitaxial InP solar cell structures

High-efficiency, heteroepitaxial (HE) InP solar cells, grown on GaAs, Si or Ge substrates, are desirable for their mechanically strong, light-weight and radiation-hard properties. However, dislocations, caused by lattice mismatch, currently limit the performance of the HE cells. This occurs through shunting paths across the active photovoltaic junction and by the formation of deep levels. In previous work we have demonstrated that plasma hydrogenation is an effective and stable means to passivate the electrical activity of dislocations in specially designed HE InP test structures. In this work, we present the first report of successful hydrogen passivation in actual InP cell structures grown on GaAs substrates by metalorganic chemical vapor deposition (MOCVD). We have found that a 2 hour exposure to a 13.56 MHz hydrogen plasma at 275 C reduces the deep level concentration in HE n+n InP cell structures from as-grown values of approximately 10(exp 15)/cm(exp -3), down to 1-2 x 10(exp 13)/cm(exp -3). The deep levels in the p-type base region of the cell structure match those of our earlier p-type test structures, which were attributed to dislocations or related point defect complexes. All dopants were successfully reactivated by a 400 C, 5 minute anneal with no detectable activation of deep levels. I-V analysis indicated a subsequent approximately 10 fold decrease in reverse leakage current at -1 volt reverse bias, and no change in the forward biased series resistance of the cell structure which indicates complete reactivation of the n+ emitter. Furthermore, electrochemical C-V profiling indicates greatly enhanced passivation depth, and hence hydrogen diffusion, for heteroepitaxial structures when compared with identically processed homoepitaxial n+p InP structures. An analysis of hydrogen diffusion in dislocated InP will be discussed, along with comparisons of passivation effectiveness for n+p versus p+n heteroepitaxial cell configurations. Preliminary hydrogen-passivated HE InP cell results will also be presented.

Chatterjee, B.↗

NASA NTRS1985

Thermal stress cycling of GaAs solar cells

A thermal cycling experiment was performed on GaAs solar cells to establish the electrical and structural integrity of these cells under the temperature conditions of a simulated low-Earth orbit of 3-year duration. Thirty single junction GaAs cells were obtained and tests were performed to establish the beginning-of-life characteristics of these cells. The tests consisted of cell I-V power output curves, from which were obtained short-circuit current, open circuit voltage, fill factor, and cell efficiency, and optical micrographs, spectral response, and ion microprobe mass analysis (IMMA) depth profiles on both the front surfaces and the front metallic contacts of the cells. Following 5,000 thermal cycles, the performance of the cells was reexamined in addition to any factors which might contribute to performance degradation. It is established that, after 5,000 thermal cycles, the cells retain their power output with no loss of structural integrity or change in physical appearance.

Janousek, B. K.↗

NASA NTRS1986

Proposal for superstructure based high efficiency photovoltaics

A novel class of cascade structures is proposed which features multijunction upper subcells, referred to as superstructure high-efficiency photovoltaics (SHEPs). The additional junctions enhance spectral response and improve radiation tolerance by reducing bulk recombination losses. This is important because ternary III-V alloys, which tend to have short minority-carrier diffusion lengths, are the only viable materials for the high-bandgap upper subcells required for cascade solar cells. Realistic simulations of AlGaAs SHEPs show that one-sun AM0 efficiencies in excess of 26 percent are possible.

Wagner, M.↗

NASA NTRS1980

Development of simplified process for environmentally resistant cells

This report describes a program to develop a simple, foolproof, all vacuum solar cell manufacturing process which can be completely automated and which results in medium efficiency cells which are inherently environmentally resistant. All components of the completed cells are integrated into a monolithic structure with no material interfaces. The exposed materials (SI, Al2O3, Al, Ni) are all resistant to atmospheric attack and the junction, per se, is passivated to prevent long term degradation. Such cells are intended to be incorporated into a simple module consisting basically of a press formed metallic superstructure with a separated glass cover for missile, etc., protection.

King, W. J.↗

NASA NTRS1983

Gallium arsenide single crystal solar cell structure and method of making

A production method and structure for a thin-film GaAs crystal for a solar cell on a single-crystal silicon substrate (10) comprising the steps of growing a single-crystal interlayer (12) of material having a closer match in lattice and thermal expansion with single-crystal GaAs than the single-crystal silicon of the substrate, and epitaxially growing a single-crystal film (14) on the interlayer. The material of the interlayer may be germanium or graded germanium-silicon alloy, with low germanium content at the silicon substrate interface, and high germanium content at the upper surface. The surface of the interface layer (12) is annealed for recrystallization by a pulsed beam of energy (laser or electron) prior to growing the interlayer. The solar cell structure may be grown as a single-crystal n.sup.+ /p shallow homojunction film or as a p/n or n/p junction film. A Ga(Al)AS heteroface film may be grown over the GaAs film.

Stirn, Richard J.↗

NASA NTRS2016

Final Mission and Navigation Design for the 2016 Mars InSight Mission

Project Overview: NASA’s 12th Discovery Program mission that will place a single geophysical lander on Mars to study its deep interior using seismic (tidal, marsquake, and impact), rotational, and thermal measurements -First mission to unveil the composition, structure and thermal state of martian crust, mantle and core; Rebuild of the Phoenix flight system, upgraded with Juno/GRAIL avionics -Phoenix cruise stage: 3-axis stabilized, 3.2 square meter UTJ (Ultra Triple-Junction) solar array, X-band telecom -Phoenix aeroshell (heat shield, backshell, parachute) -Phoenix lander: radar, pulsed thrusters, legs, payload deck, 5.1 square meter UTJ solar arrays, two redundant Li-ion batteries, UHF (Ultra High Frequency)/X-band telecom -Dual string: Internally or functionally-redundant equipment; Science Payload -SEIS (Seismic Experiment for Interior Structure) / CNES (Centre National d’Etudes Spatiales); Three-axis seismometry, to measure seismic waves traveling through the interior -HP3 (Heat Flow and Physical Properties Probe) / DLR (German Aerospace Center) -Subsurface heat probe, to measure the heat flux from the interior - RISE (Rotation and Interior Structure Experiment) / JPL (Jet Propulsion Laboratory) -Radiometric geodesy, to determine precession & nutation of the planet’s rotation axis. 2016 Disclaimer: The InSight launch in 2016 was suspended due to critical issues with the Seismic Experiment for Interior Structure (SEIS) instrument that could not be fixed prior to the planned launch period. This presentation and its corresponding paper represent the state of the design for the 2016 mission. No attempt has been made to reflect the latest developments. [2018 Note: InSight (Mars Lander) was later launched and arrived on Mars on Nov. 26, 2018.]

Abilleira, F.↗

NASA NTRS2007

GaAs Photovoltaics on Polycrystalline Ge Substrates

High efficiency III-V multijunction solar cells deposited on metal foil or even polymer substrates can provide tremendous advantages in mass and stowage, particularly for planetary missions. As a first step towards that goal, poly-crystalline p/i/n GaAs solar cells are under development on polycrystalline Ge substrates. Organo Metallic Vapor Phase Epitaxy (OMVPE) parameters for pre-growth bake, nucleation and deposition have been examined. Single junction p/i/n GaAs photovoltaic devices, incorporating InGaP front and back window layers, have been grown and processed. Device performance has shown a dependence upon the thickness of a GaAs buffer layer deposited between the Ge substrate and the active device structure. A thick (2 m) GaAs buffer provides for both increased average device performance as well as reduced sensitivity to variations in grain size and orientation. Illumination under IR light (lambda > 1 micron), the cells showed a Voc, demonstrating the presence of an unintended photoactive junction at the GaAs/Ge interface. The presence of this junction limited the efficiency to approx.13% (estimated with an anti-refection coating) due to the current mismatch and lack of tunnel junction interconnect.

Wilt, David M.↗

NASA NTRS1976

Improved GaAs solar cells with very thin junctions

Violet cells with 500-1000 A junction depths have been made in GaAs by narrow junction diffusion followed by anodization. The best AM0 efficiencies obtained by this technique have been 10.5% (14% at AM1). GaAlAs-GaAs structures with very thin GaAlAs layers are much more promising, and efficiencies of over 18% at AM0 have been measured (21.9% at AM1).

Hovel, H. J.↗

NASA NTRS1992

Modelling and performance of Nb SIS mixers in the 1.3 mm and 0.8 mm bands

We describe the modeling and subsequent improvements of SIS waveguide mixers for the 200-270 and 330-370 GHz bands (Blundell, Carter, and Gundlach 1988, Carter et al 1991). These mixers are constructed for use in receivers on IRAM radiotelescopes on Pico Veleta (Spain, Sierra Nevada) and Plateau de Bure (French Alps), and must meet specific requirements. The standard reduced height waveguide structure with suspended stripline is first analyzed and a model is validated through comparison with scale model and working scale measurements. In the first step, the intrinsic limitations of the standard mixer structure are identified, and the parameters are optimized bearing in mind the radioastronomical applications. In the second step, inductive tuning of the junctions is introduced and optimized for minimum noise and maximum bandwidth. In the 1.3 mm band, a DSB receiver temperature of less than 110 K (minimum 80 K) is measured from 180 through 260 GHz. In the 0.8 mm band, a DSB receiver temperature of less than 250 K (minimum 175 K) is obtained between 325 and 355 GHz. All these results are obtained with room-temperature optics and a 4 GHz IF chain having a 500 MHz bandwidth and a noise temperature of 14 K.

Karpov, A.↗

NASA NTRS1996

Structural Concepts Study of Non-circular Fuselage Configurations

A preliminary study of structural concepts for noncircular fuselage configurations is presented. For an unconventional flying-wing type aircraft, in which the fuselage is inside the wing, multiple fuselage bays with non-circular sections need to be considered. In a conventional circular fuselage section, internal pressure is carried efficiently by a thin skin via hoop tension. If the section is non-circular, internal pressure loads also induce large bending stresses. The structure must also withstand additional bending and compression loads from aerodynamic and gravitational forces. Flat and vaulted shell structural configurations for such an unconventional, non-circular pressurized fuselage of a large flying-wing were studied. A deep honeycomb sandwich-shell and a ribbed double-wall shell construction were considered. Combinations of these structural concepts were analyzed using both analytical and simple finite element models of isolated sections for a comparative conceptual study. Weight, stress, and deflection results were compared to identify a suitable configuration for detailed analyses. The flat sandwich-shell concept was found preferable to the vaulted shell concept due to its superior buckling stiffness. Vaulted double-skin ribbed shell configurations were found to be superior due to their weight savings, load diffusion, and fail-safe features. The vaulted double-skin ribbed shell structure concept was also analyzed for an integrated wing-fuselage finite element model. Additional problem areas such as wing-fuselage junction and pressure-bearing spar were identified.

Mukhopadhyay, Vivel↗

NASA NTRS1995

Measurements of noise in Josephson-effect mixers

We present new heterodyne receiver results obtained at 100 GHz using resistively-shunted Nb and NbN tunnel junctions. In addition, we have carried out accurate measurements of the available noise power of these devices at the L-band (1.5 GHz) IF (infrasonic) frequency. Both the heterodyne and the output noise measurements show that the noise of these devices can be a factor of five or more higher than that predicted by the simple current-biased RSJ model. The noise approaches the appropriate thermal or thermal and shot noise limits for bias voltages where the nonlinearity is not strong (i.e., V greater than I(sub C)R(sub N)), but as expected from the RSJ model, can be significantly higher at the low voltages where the mixers are typically biased. The bias voltage dependence of the noise shows structure which is associated with resonances in the RF embedding circuit. Surprisingly, we find that changes in the high-frequency (100 GHz) impedance presented to the junction can dramatically affect the magnitude and voltage dependence of the low-frequency (1.5 GHz) noise. This emphasizes the necessity of very closely matching the junction to free space over a wide frequency range.

NOISE MEASUREMENT↗

NASA NTRS1975

Studies of silicon PN junction solar cells

Silicon pn junction solar cells made with low-resistivity substrates show poorer performance than traditional theory predicts. The purpose of this research was to identify and characterize the physical mechanisms responsible for the discrepancy. Attention was concentrated on the open circuit voltage in shallow junction cells of 0.1 ohm-cm substrate resistivity. A number of possible mechanisms that can occur in silicon devices were considered. Two mechanisms which are likely to be of main importance in explaining the observed low values of open-circuit voltage were found: (1) recombination losses associated with defects introduced during junction formation, and (2) inhomogeneity of defects and impurities across the area of the cell. To explore these theoretical anticipations, various diode test structures were designed and fabricated and measurement configurations for characterizing the defect properties and the areal inhomogeneity were constructed.

Lindholm, F. A.↗

NASA NTRS1986

High band gap 2-6 and 3-5 tunneling junctions for silicon multijunction solar cells

A multijunction silicon solar cell of high efficiency is provided by providing a tunnel junction between the solar cell junctions to connect them in series. The tunnel junction is comprised of p+ and n+ layers of high band gap 3-5 or 2-6 semiconductor materials that match the lattice structure of silicon, such as GaP (band gap 2.24 eV) or ZnS (band gap 3.6 eV). Each of which has a perfect lattice match with silicon to avoid defects normally associated with lattice mismatch.

Daud, Taher↗

NASA NTRS1991

Thin, Lightweight Solar Cell

Improved design for thin, lightweight solar photovoltaic cells with front contacts reduces degradation of electrical output under exposure to energetic charged particles (protons and electrons). Increases ability of cells to maintain structural integrity under exposure to ultraviolet radiation by eliminating ultraviolet-degradable adhesives used to retain cover glasses. Interdigitated front contacts and front junctions formed on semiconductor substrate. Mating contacts formed on back surface of cover glass. Cover glass and substrate electrostatically bonded together.

Brandhorst, Henry W., Jr.↗

NASA NTRS1991

YBa2Cu3O(7-x)/Au/Nb device structures

Fabrication and testing of planar and edge geometry YBaCuO/Au/Nb superconductor/normal-metal/superconductor (SNS) device structures is described. Weak-link devices of this type serve as sensitive probes of the electrical quality of the YBaCuO/Au interface. The devices are fabricated using laser-ablated, in situ, c-axis-oriented YBaCuO thin films, with both annealed and unannealed YBaCuO/Au interfaces. The planar SNS structures are formed by sequential, in situ deposition of YBaCuO, Au, and Nb, followed by etching, planarization, and wiring electrode definition to produce junctions ranging from 5 to 20 micron on a side. Resulting RnA products are 1-10 x 10 to the -8th ohm-sq cm with critical current densities up to 5 kA/sq cm. For the edge geometry devices, the YBaCuO film edges are patterned using Ar ion milling, followed by a low energy ion cleaning step and in situ deposition of Au and Nb. Devices with areas in the 10 to the -7th to 10 to the -8th sq cm range have been fabricated with RnA products lower than 10 to the -8th ohm-sq cm and critical current densities up to 3kA/sq cm. Both types of devices show ac Josephson steps under microwave irradiation. The best results have been obtained with annealed YBaCuO/Au interfaces.

Hunt, B. D.↗

NASA NTRS2009

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗

NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗

NASA NTRS1976

Translatory shock absorber for attitude sensors

A translatory shock absorber is provided for mounting an attitude sensor thereon for isolating a sensor from translatory vibrations. The translatory shock absorber includes a hollow block structure formed as one piece to form a parallelogram. The absorber block structure includes a movable top plate for supporting the attitude sensor and a fixed base plate with opposed side plates interposed between. At the junctions of the side plates, and the base and top plates, there are provided grooves which act as flexible hinges for attenuating translatory vibrations. A damping material is supported on a pedestal which is carried on the base plate between the side plates thereof. The top of the damping material rests against the bottom surface of the top plate for eliminating the resonant peaks of vibration.

Vonpragenau, G. L.↗