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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

F-15 digital electronic engine control system description

A digital electronic engine control (DEEC) was developed for use on the F100-PW-100 turbofan engine. This control system has full authority control, capable of moving all the controlled variables over their full ranges. The digital computational electronics and fault detection and accomodation logic maintains safe engine operation. A hydromechanical backup control (BUC) is an integral part of the fuel metering unit and provides gas generator control at a reduced performance level in the event of an electronics failure. The DEEC's features, hardware, and major logic diagrams are described.

Myers, L. P.↗
NASA NTRS1992

Interface For Dual-Channel MIL-STD-1553 Data Bus

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

Davies, Bryan L.↗
NASA NTRS1980

DDL:Digital systems design language

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

Shival, S. G.↗
DOE OSTI2022

Event driven readout architecture with non-priority arbitration for radiation detectors

A novel event driven readout architecture, EDWARD (Event Driven with Access and 8 Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz' arbiters, removing the need for an imposed prioritization scheme. It also provides protection against glitches during readout. The system allows not only reading pixel activities, but also retrieving additional data, both analog and digital, from the pixels. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal, seen as an acknowledge token, so there is no dead time between readouts.

47 OTHER INSTRUMENTATION↗
NASA NTRS1980

Biased-receiver digital interface

Coupling circuits converts TTL signals to higher voltage, higher current logic with good noise rejection. Depending on selected components, circuit may also be adapted to low-power applications.

Fitzgerald, F. C.↗
NASA NTRS1977

Memory device for two-dimensional radiant energy array computers

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

Schaefer, D. H.↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
NASA NTRS1979

Problems in processing multizonal video information at specialized complexes

Architectural requirements of a minicomputer-based specialized complex for automated digital analysis of multizonal video data are examined. The logic structure of multizonal video data and the complex mathematical provision required for the analysis of such data are described. The composition of the specialized complex, its operating system, and the required set of peripheral devices are discussed. It is noted that although much of the analysis can be automated, the operator-computer dialog mode is essential for certain stages of the analysis.

Shamis, V. A.↗
NASA NTRS2004

IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA

Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.

single event upset (SEU)↗
NASA NTRS2004

Digital design using selection operations

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Whitaker, Sterling R.↗
DOE OSTI2023

Performance and Commissioning of the BigBite Timing Hodoscope for Nucleon Form Factor Measurements at Jefferson Lab

The BigBite Timing Hodoscope detector is the primary subject of this thesis. The Super BigBite Spectrometer is a Jefferson Lab Hall A Collaboration project that has and will continue to measure nucleon electromagnetic form factors. This spectrometer includes the Timing Hodoscope which provides high resolution particle timing data for scattered electrons in the electron arm of BigBite. The Timing Hodoscope utilizes 90, 25 × 25 × 600 mm3 scintillator bars stacked on top of each other to form a single detector plane, and these bars are connected to 180 photo-multiplier tubes via light guides. Particles collide with the scintillating material creating a shower of optical photons and these particle events in the bars are collected to generate signals that are readout by the data acquisition (DAQ) electronics. NINO ASIC amplifier-discriminator cards output signals from the photo-multiplier tubes into analogue and logic signals, which are sent to analogue-to-digital (ADC) and time-to-digital (TDC) converter data acquisition readout modules. This data is then used for analysis of the detector. The focus of this thesis is the construction, commissioning, calibration, and performance of the BigBite Timing Hodoscope before and during the first of five nucleon electromagnetic form factor experiments at Jefferson Lab Hall A. Before the neutron magnetic form factor, G n M, experiment, cosmic ray data was collected during commissioning to confirm proper operation of the Timing Hodoscope electronics by observing the ADC and TDC data. Commissioning studies for charge normalization, gain matching, and other ADC and TDC detector data variables were performed before moving the detector into Hall A. Following installation in Hall A, several calibration studies were implemented to fine-tune the detector in preparation for use in the experiment. The calibration studies included analysis of timing cuts, TDC alignment, the time-walk effect, time difference offsets, and scintillator velocity corrections. Once the Timing Hodoscope was well-calibrated, data-taking during the experiment commenced and the beam-on-target data was used to characterize the Timing Hodoscope performance during the G n M experiment run-time. The performance analysis included studies observing energy deposit, cluster size, rates, accidentals, pile-up, tracking efficiency, position resolution, and time resolution. After application of physics cuts to ensure a data set comprised of particle tracks corresponding to elastic electrons, which is the main data of interest for measurement of G n M, the Timing Hodoscope is shown on average across all kinematic settings to have a >98% tracking efficiency, a position resolution of 4-6 cm in the non-dispersive plane and 1.5-2 cm in the dispersive plane, and a time resolution of 500-750 ps. These performance results are compared to a GEANT4 based performance simulation of the BigBite Timing Hodoscope for reference, showing to what degree the measured performance values match those taken from the simulation.

Marinaro, Ralph↗
DOE OSTI2024

Calibration of the analog beam-signal hardware for the credited engineered beam power limit system at the Proton Power Upgrade Project at the Spallation Neutron Source

A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).

Bobrek, Miljko↗
NASA NTRS1977

Standard high-reliability integrated circuit logic packaging

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

Slaughter, D. W.↗
DOE OSTI2025

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗
NASA NTRS1982

Advanced reliability modeling of fault-tolerant computer-based systems

Two methodologies for the reliability assessment of fault tolerant digital computer based systems are discussed. The computer-aided reliability estimation 3 (CARE 3) and gate logic software simulation (GLOSS) are assessment technologies that were developed to mitigate a serious weakness in the design and evaluation process of ultrareliable digital systems. The weak link is based on the unavailability of a sufficiently powerful modeling technique for comparing the stochastic attributes of one system against others. Some of the more interesting attributes are reliability, system survival, safety, and mission success.

Bavuso, S. J.↗
NASA NTRS1993

WNN 92; Proceedings of the 3rd Workshop on Neural Networks: Academic/Industrial/NASA/Defense, Auburn Univ., AL, Feb. 10-12, 1992 and South Shore Harbour, TX, Nov. 4-6, 1992

The present conference discusses such neural networks (NN) related topics as their current development status, NN architectures, NN learning rules, NN optimization methods, NN temporal models, NN control methods, NN pattern recognition systems and applications, biological and biomedical applications of NNs, VLSI design techniques for NNs, NN systems simulation, fuzzy logic, and genetic algorithms. Attention is given to missileborne integrated NNs, adaptive-mixture NNs, implementable learning rules, an NN simulator for travelling salesman problem solutions, similarity-based forecasting, NN control of hypersonic aircraft takeoff, NN control of the Space Shuttle Arm, an adaptive NN robot manipulator controller, a synthetic approach to digital filtering, NNs for speech analysis, adaptive spline networks, an anticipatory fuzzy logic controller, and encoding operations for fuzzy associative memories.

Padgett, Mary L.↗
DOE OSTI2021

UEMtomaton: A Source-Available Platform to Aid in Start-up of Ultrafast Electron Microscopy Labs

The steady rise in the number of ultrafast electron microscopy (UEM) labs, in addition to the opacity and lack of detailed descriptions of current approaches that would enable point-by-point construction, has created an opportunity for sharing common methods and instrumentation for (for example) automating data acquisition to assist in efficient lab start-up and to learn about common and robust protocols. In the spirit of open sharing of methods, we provide here a description of an entry-level method and user interface (UI) for automating UEM experiments, and we provide access to the source code and scripts (source-available) for ease of implementation or as a starting reference point for those entering or seeking to enter the field (https://github.com/CEMSFlannigan/UEMtomaton/releases/tag/v1.0). Core instrumentation and physical connections in the UEM lab at Minnesota are described. Interface communication schemes consisting of duo server-client pairs between critical components – the optical delay stage and the UEM digital camera – are presented, with emphasis placed on describing the logic and communications sequence designed to conduct automated series acquisitions. An application designed and programmed with C++/CLI as Windows Forms in Microsoft Visual Studio – dubbed UEMtomaton – is also presented. Key to the UI layout is centralization of the automation tasks and establishment of communication within the software rather than by interfacing with each individual workstation. It is our hope that this note provides useful insight for current and future UEM researchers, particularly with respect to generalizability and portability of the approach to emerging labs. Here, we note that while this basic, entry-level approach is certainly not the most sophisticated or comprehensive of those currently in use, we feel there is nevertheless value in clearly communicating a proven straightforward method to hopefully lower the barrier to entry into the field.

47 OTHER INSTRUMENTATION↗