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Computer processing procedures and programs applied to Multispectral Scanner data from LANDSAT are described. The output product produced is a level 1 land use map in conformance with a Universal Transverse Mercator projection. The region studied was a five-county area in north Alabama.
For abstract, see N78-25123.
The use of an array processor as a computational element in rotorcraft real-time simulation is studied. A multilooping scheme was considered in which the rotor would loop over its calculations a number of time while the remainder of the model cycled once on a host computer. To prove that such a method would realistically simulate rotorcraft, a FORTRAN program was constructed to emulate a typical host-array processor computing configuration. The multilooping of an expanded rotor model, which included appropriate kinematic equations, resulted in an accurate and stable simulation.
The computing equipment in the engineering systems simulation laboratory of the Houston University Cullen College of Engineering is described and its advantages are summarized. The application of computer techniques in aerospace-related research psychology and in chemical, civil, electrical, industrial, and mechanical engineering is described in abstracts of 84 individual projects and in reprints of published reports. Research supports programs in acoustics, energy technology, systems engineering, and environment management as well as aerospace engineering.
Additions made to the original version of the DISCOS computer programs are presented. They include demonstrations of problems and improved capabilities. Remarks are made pertaining new subroutines.
A Central Control Element (CCE) module which controls the Automatically Reconfigurable Modular System (ARMS) and allows both redundant processing and multi-computing in the same computer with real time mode switching, is discussed. The same hardware is used for either reliability enhancement, speed enhancement, or for a combination of both.
The US Army Fault-Tolerant Architecture (AFTA) has been defined to meet real-time fault-tolerant processing requirements of future Army applications. AFTA is the enabling technology that will allow the Army to configure existing processors and other hardware to provide high throughput and ultrahigh reliability necessary for terrain-following/terrain-avoidance (TF/TA) and nap-of-the-earth (NOE) flight control and other advanced Army applications. A brief description of AFTA's relevant attributes and theory of operation is given. The systems engineering models which permit the configuration on an AFTA to meet mission requirements as they evolve are presented, along with an example of their use to engineer an AFTA configuration. The resulting AFTA configuration, its predicted throughput, reliability, availability, weight, power, volume, and life-cycle cost impact, and the effects of possible engineering tradeoffs are presented.
Digital computers for interplanetary spacecraft, comparing centralized and decentralized approaches for implementing onboard functions
Digital attenuator system design for hybrid computers
Digital optical computer design has been focused primarily towards parallel (single point-to-point interconnection) implementation. This architecture is compared to currently developing VHSIC systems. Using demonstrated multichannel acousto-optic devices, a figure of merit can be formulated. The focus is on a figure of merit termed Gate Interconnect Bandwidth Product (GIBP). Conventional parallel optical digital computer architecture demonstrates only marginal competitiveness at best when compared to projected semiconductor implements. Global, analog global, quasi-digital, and full digital interconnects are briefly examined as alternative to parallel digital computer architecture. Digital optical computing is becoming a very tough competitor to semiconductor technology since it can support a very high degree of three dimensional interconnect density and high degrees of Fan-In without capacitive loading effects at very low power consumption levels.
Digital partitioning offers a flexible means of increasing the accuracy of an optical matrix-vector processor. This algorithm can be implemented with the same architecture required for a purely analog processor, which gives optical matrix-vector processors the ability to perform high-accuracy calculations at speeds comparable with or greater than electronic computers as well as the ability to perform analog operations at a much greater speed. Digital partitioning is compared with digital multiplication by analog convolution, residue number systems, and redundant number representation in terms of the size and the speed required for an equivalent throughput as well as in terms of the hardware requirements. Digital partitioning and digital multiplication by analog convolution are found to be the most efficient alogrithms if coding time and hardware are considered, and the architecture for digital partitioning permits the use of analog computations to provide the greatest throughput for a single processor.
Advanced digital computer design for spacecraft
Fourier series digital computer simulation of tape recording process - signal detection in prescence of white Gaussian noise
Digital correlation for computing sensitivity coefficients on iterative analog computer
Computer aided digital systems design with combinatorial logic elements
The Digital Optical Computing Program within the National Science Foundation Engineering Research Center for Opto-electronic Computing Systems has as its specific goal research on optical computing architectures suitable for use at the highest possible speeds. The program can be targeted toward exploiting the time domain because other programs in the Center are pursuing research on parallel optical systems, exploiting optical interconnection and optical devices and materials. Using a general purpose computing architecture as the focus, we are developing design techniques, tools and architecture for operation at the speed of light limit. Experimental work is being done with the somewhat low speed components currently available but with architectures which will scale up in speed as faster devices are developed. The design algorithms and tools developed for a general purpose, stored program computer are being applied to other systems such as optimally controlled optical communication networks.
Space digital computer design fulfilling requirements of efficiency, sophistication, weight and power, discussing reliability optimization and hardware redundancy
Complex digital computers designed for Apollo spacecraft missions, discussing construction techniques