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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Prototype Common Bus Spacecraft: Hover Test Implementation and Results

In order to develop the capability to evaluate control system technologies, NASA Ames Research Center (Ames) began a test program to build a Hover Test Vehicle (HTV) - a ground-based simulated flight vehicle. The HTV would integrate simulated propulsion, avionics, and sensors into a simulated flight structure, and fly that test vehicle in terrestrial conditions intended to simulate a flight environment, in particular for attitude control. The ultimate purpose of the effort at Ames is to determine whether the low-cost hardware and flight software techniques are viable for future low cost missions. To enable these engineering goals, the project sought to develop a team, processes and procedures capable of developing, building and operating a fully functioning vehicle including propulsion, GN&C, structure, power and diagnostic sub-systems, through the development of the simulated vehicle.

Hine, Butler Preston↗
NASA NTRS1993

Application of new electro-optic technology to Space Station Freedom data management system

A low risk design methodology to permit the local bus structures to support increased data carrying capacities and to speed messages and data flow between nodes or stations on the Space Station Freedom Data Management System in anticipation of growing requirements was evaluated and recommended. The recommended design employs a collateral fiber optic technique that follows a NATO avionic standard that is developed, tested, and available. Application of this process will permit a potential 25 fold increase in data transfer performance on the local wire bus network with a fiber optic network, maintaining the functionality of the low-speed bus and supporting all of the redundant transmission and fault detection capabilities designed into the existing system. The application of wavelength division multiplexing (WDM) technology to both the local data bus and global data bus segments of the Data Management System to support anticipated additional highspeed data transmission requirements was also examined. Techniques were examined to provide a dual wavelength implementation of the fiber optic collateral networks. This dual wavelength implementation would permit each local bus to support two simultaneous high-speed transfers on the same fiber optic bus structure and operate within the limits of the existing protocol standard. A second WDM study examined the use of spectral sliced technology to provide a fourfold increase in the Fiber Distributed Data Interface (FDDI) global bus networks without requiring modifications to the existing installed cable plant. Computer simulations presented indicated that this data rate improvement can be achieved with commercially available optical components.

Husbands, C. R.↗
NASA NTRS1994

Modular Cooling Components

Three modular heat-transfer components designed for use together or separately. Simple mechanical connections facilitate assembly of these and related heat-transfer components into cooling systems of various configurations, such as to cool laboratory equipment rearranged for different experiments. Components are clamp-on cold plate, cold plate attached to flexible heat pipe, and thermal-bus receptacle. Clamp-on cold plate moved to any convenient location for attachment of equipment cooled by it, then clamped onto thermal bus. Heat from equipment conducted through plate and into coolant. Thermal-bus receptacle integral with thermal bus. Includes part of thermal bus to which clamp-on cold plate attached, plus tapered socket into which condenser end of flexible heat pipe plugged. Thermal-bus receptacle includes heat-pipe wick structure using coolant in bus to enhance transfer of heat from cold plate.

Eastman, G. Yale↗
NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗
NASA NTRS2008

Cluster Inter-Spacecraft Communications

A document describes a radio communication system being developed for exchanging data and sharing data-processing capabilities among spacecraft flying in formation. The system would establish a high-speed, low-latency, deterministic loop communication path connecting all the spacecraft in a cluster. The system would be a wireless version of a ring bus that complies with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus enhancement to the IEEE standard developed at NASA's Jet Propulsion Laboratory). Every spacecraft in the cluster would be equipped with a ring-bus radio transceiver. The identity of a spacecraft would be established upon connection into the ring bus, and the spacecraft could be at any location in the ring communication sequence. In the event of failure of a spacecraft, the ring bus would reconfigure itself, bypassing a failed spacecraft. Similarly, the ring bus would reconfigure itself to accommodate a spacecraft newly added to the cluster or newly enabled or re-enabled. Thus, the ring bus would be scalable and robust. Reliability could be increased by launching, into the cluster, spare spacecraft to be activated in the event of failure of other spacecraft.

Cox, Brian↗
NASA NTRS2010

Smart Power Supply for Battery-Powered Systems

A power supply for battery-powered systems has been designed with an embedded controller that is capable of monitoring and maintaining batteries, charging hardware, while maintaining output power. The power supply is primarily designed for rovers and other remote science and engineering vehicles, but it can be used in any battery alone, or battery and charging source applications. The supply can function autonomously, or can be connected to a host processor through a serial communications link. It can be programmed a priori or on the fly to return current and voltage readings to a host. It has two output power busses: a constant 24-V direct current nominal bus, and a programmable bus for output from approximately 24 up to approximately 50 V. The programmable bus voltage level, and its output power limit, can be changed on the fly as well. The power supply also offers options to reduce the programmable bus to 24 V when the set power limit is reached, limiting output power in the case of a system fault detected in the system. The smart power supply is based on an embedded 8051-type single-chip microcontroller. This choice was made in that a credible progression to flight (radiation hard, high reliability) can be assumed as many 8051 processors or gate arrays capable of accepting 8051-type core presently exist and will continue to do so for some time. To solve the problem of centralized control, this innovation moves an embedded microcontroller to the power supply and assigns it the task of overseeing the operation and charging of the power supply assets. This embedded processor is connected to the application central processor via a serial data link such that the central processor can request updates of various parameters within the supply, such as battery current, bus voltage, remaining power in battery estimations, etc. This supply has a direct connection to the battery bus for common (quiescent) power application. Because components from multiple vendors may have differing power needs, this supply also has a secondary power bus, which can be programmed a priori or on-the-fly to boost the primary battery voltage level from 24 to 50 V to accommodate various loads as they are brought on line. Through voltage and current monitoring, the device can also shield the charging source from overloads, keep it within safe operating modes, and can meter available power to the application and maintain safe operations.

Krasowski, Michael J.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS1972

Fault tolerant data management system

Described in detail are: (1) results obtained in modifying the onboard data management system software to a multiprocessor fault tolerant system; (2) a functional description of the prototype buffer I/O units; (3) description of modification to the ACADC and stimuli generating unit of the DTS; and (4) summaries and conclusions on techniques implemented in the rack and prototype buffers. Also documented is the work done in investigating techniques of high speed (5 Mbps) digital data transmission in the data bus environment. The application considered is a multiport data bus operating with the following constraints: no preferred stations; random bus access by all stations; all stations equally likely to source or sink data; no limit to the number of stations along the bus; no branching of the bus; and no restriction on station placement along the bus.

Gustin, W. M.↗
NASA NTRS1987

Digital Autonomous Terminal Access Communication (DATAC) system

In order to accommodate the increasing number of computerized subsystems aboard today's more fuel efficient aircraft, the Boeing Co. has developed the DATAC (Digital Autonomous Terminal Access Control) bus to minimize the need for point-to-point wiring to interconnect these various systems, thereby reducing total aircraft weight and maintaining an economical flight configuration. The DATAC bus is essentially a local area network providing interconnections for any of the flight management and control systems aboard the aircraft. The task of developing a Bus Monitor Unit was broken down into four subtasks: (1) providing a hardware interface between the DATAC bus and the Z8000-based microcomputer system to be used as the bus monitor; (2) establishing a communication link between the Z8000 system and a CP/M-based computer system; (3) generation of data reduction and display software to output data to the console device; and (4) development of a DATAC Terminal Simulator to facilitate testing of the hardware and software which transfer data between the DATAC's bus and the operator's console in a near real time environment. These tasks are briefly discussed.

Novacki, Stanley M., III↗
NASA NTRS1996

Fault-tolerant processing system

A fault-tolerant, fiber optic interconnect, or backplane, which serves as a via for data transfer between modules. Fault tolerance algorithms are embedded in the backplane by dividing the backplane into a read bus and a write bus and placing a redundancy management unit (RMU) between the read bus and the write bus so that all data transmitted by the write bus is subjected to the fault tolerance algorithms before the data is passed for distribution to the read bus. The RMU provides both backplane control and fault tolerance.

Palumbo, Daniel L.↗
NASA NTRS2001

Multiple output power supply circuit for an ion engine with shared upper inverter

A power supply circuit for an ion engine suitable for a spacecraft is coupled to a bus having a bus input and a bus return. The power supply circuit has a first primary winding of a first transformer. An upper inverter circuit is coupled to the bus input and the first primary winding. The power supply circuit further includes a first lower inverter circuit coupled to the bus return and the first primary winding. The second primary winding of a second transformer is coupled to the upper inverter circuit. A second lower inverter circuit is coupled to the bus return and the second primary winding.

Cardwell, Jr., Gilbert I.↗