Forecasting Smart Grid Load on the Wire
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Under the Department of Energy’s Light Water Reactor Sustainability Program, within the Plant Modernization research pathway, the Digital I&C Qualification Project is identifying new methods that would be beneficial in qualifying digital I&C systems and devices for safety-related usage. One such method that would be useful in qualifying field components such as sensors and actuators is the concept of testability. The Nuclear Regulatory Commission (NRC) considers testability to be one of two design attributes sufficient to eliminate consideration of software-based or software logic-based common cause failure (the other being diversity). The NRC defines acceptable “testability” as follows: Testability – A system is sufficiently simple such that every possible combination of inputs and every possible sequence of device states are tested and all outputs are verified for every case (100% tested). [NUREG 0800, Chapter 7, Branch Technical Position (BTP) 7-19] This qualification method has never proven to be practical in view of the very large number of combinations of inputs and sequences of device states for a typical I&C device. However, many of these combinations are not unique in the sense that they represent the same state space or in that that they represent state space that would not affect the critical design basis functions of the device. Therefore, the state space of interest might possibly be reduced to a manageable dimension through such analysis. This project will focus on a representative I&C device similar in design, function, and complexity to the types of devices that would likely be deployed in nuclear power plants as digital or software based sensors and actuators (e.g. Smart Sensors). Analysis will be conducted to determine the feasibility of testing this device in a manner consistent with the NRC definition. This report describes the development of test process for Bounded Exhaustive Testing with respect to Combinatorial Test (CT) methods. The report describes the candidate Device Under Test SW – the VCU smart sensor, conceptual experimental methods for stated test objectives, description of the process, tools, resources, and computing. This information will be used to fully develop a detailed test plan (based on statistical measure needs) and test environment for conducting an I&C device testability demonstration study. The future planed experimental study of this project is to demonstrate digital qualification via Bounded Exhaustive Testability with respect to Common Cause Failure.
The Chicago Array of Things (AoT) project, funded by the US National Science Foundation, created an experimental, urban-scale measurement capability to support diverse scientific studies. Initially conceived as a traditional sensor network, collaborations with many science communities guided the project to design a system that is remotely programmable to implement Artificial Intelligence (AI) within the devices-at the “edge” of the network-as a means for measuring urban factors that heretofore had only been possible with human observers, such as human behavior including social interaction. The concept of “software-defined sensors” emerged from these design discussions, opening new possibilities, such as stronger privacy protections and autonomous, adaptive measurements triggered by events or conditions. We provide examples of current and planned social and behavioral science investigations uniquely enabled by software-defined sensors as part of the SAGE project, an expanded follow-on effort that includes AoT.
The IEEE 1451.1 Standard for a Smart Transducer Interface defines a common network information model for connecting and managing smart elements in control and data acquisition networks using network-capable application processors (NCAPs). The Standard is a network-neutral design model that is easily ported across operating systems and physical networks for implementing complex acquisition and control applications by simply plugging in the appropriate network level drivers. To simplify configuration and tracking of transducer and actuator details, the family of 1451 standards defines a Transducer Electronic Data Sheet (TEDS) that is associated with each physical element. The TEDS contains all of the pertinent information about the physical operations of a transducer (such as operating regions, calibration tables, and manufacturer information), which the NCAP uses to configure the system to support a specific transducer. The Integrated Systems Health Management (ISHM) group at NASA's John C. Stennis Space Center (SSC) has been developing an ISHM architecture that utilizes IEEE 1451.1 as the primary configuration and data acquisition mechanism for managing and collecting information from a network of distributed intelligent sensing elements. This work has involved collaboration with other NASA centers, universities and aerospace industries to develop IEEE 1451.1 compliant sensors and interfaces tailored to support health assessment of complex systems. This paper and presentation describe the development and implementation of an interface for the configuration, management and communication of data, information and knowledge generated by a distributed system of IEEE 1451.1 intelligent elements monitoring a rocket engine test system. In this context, an intelligent element is defined as one incorporating support for the IEEE 1451.x standards and additional ISHM functions. Our implementation supports real-time collection of both measurement data (raw ADC counts and converted engineering units) and health statistics produced by each intelligent element. The handling of configuration, calibration and health information is automated by using the TEDS in combination with other electronic data sheets extensions to convey health parameters. By integrating the IEEE 1451.1 Standard for a Smart Transducer Interface with ISHM technologies, each element within a complex system becomes a highly flexible computation engine capable of self-validation and performing other measures of the quality of information it is producing.
All spacecraft require attitude determination at some level of accuracy. This can be a very coarse requirement of tens of degrees, in order to point solar arrays at the sun, or a very fine requirement in the milliarcsecond range, as required by Hubble Space Telescope. A toolbox of attitude determination methods, applicable across this wide range, has been developed over the years. There have been many advances in the thirty years since the publication of Reference, but the fundamentals remain the same. One significant change is that onboard attitude determination has largely superseded ground-based attitude determination, due to the greatly increased power of onboard computers. The availability of relatively inexpensive radiation-hardened microprocessors has led to the development of "smart" sensors, with autonomous star trackers being the first spacecraft application. Another new development is attitude determination using interferometry of radio signals from the Global Positioning System (GPS) constellation. This article reviews both the classic material and these newer developments at approximately the level of, with emphasis on. methods suitable for use onboard a spacecraft. We discuss both "single frame" methods that are based on measurements taken at a single point in time, and sequential methods that use information about spacecraft dynamics to combine the information from a time series of measurements.
The combinatorics of track seeding has long been a computational bottleneck for triggering and offline computing in High Energy Physics (HEP), and remains so for the HL-LHC. Next-generation pixel sensors will be sufficiently fine-grained to determine angular information of the charged particle passing through from pixel-cluster properties. This detector technology immediately improves the situation for offline tracking, but any major improvements in physics reach are unrealized since they are dominated by lowest-level hardware trigger acceptance. We will demonstrate track angle and hit position prediction, including errors, using a mixture density network within a single layer of silicon as well as the progress towards and status of implementing the neural network in hardware on both FPGAs and ASICs.
The combinatorics of track seeding has long been a computational bottleneck for triggering and offline computing in High Energy Physics (HEP), and remains so for the HL-LHC. Next-generation pixel sensors will be sufficiently fine-grained to determine angular information of the charged particle passing through from pixel-cluster properties. This detector technology immediately improves the situation for offline tracking, but any major improvements in physics reach are unrealized since they are dominated by lowest-level hardware trigger acceptance. We will demonstrate track angle and hit position prediction, including errors, using a mixture density network within a single layer of silicon as well as the progress towards and status of implementing the neural network in hardware on both FPGAs and ASICs.
This paper presents an optimal dispatch algorithm to coordinate customer-owned controllable loads and smart solar inverters with utility-owned voltage regulators and capacitors to meet voltage control objectives. The optimization problem is formulated as a mixed-integer nonlinear programming (MINLP) problem. A voltage sensitivity matrix (VSM) is used to linearize the effect of control actions on the voltage at customer nodes when solving the MINLP. The VSM is recalculated at each time step to improve the computational accuracy. Both discrete switching actions of the capacitor and VRs and the continuous adjustment of real and reactive power from load and smart inverters are considered in the MINLP volt-var problem formulation. The objective function minimizes the cost of all control actions and the magnitude of voltage fluctuations from the previous time period. Constraints ensure that the voltage at each node is maintained within ANSI limits and the feeder power factor is controlled within the desired range. The algorithm is tested using an actual 3-phase unbalanced distribution feeder model. Simulation results demonstrate that the proposed algorithm is computationally feasible on real circuits and improves voltage control while minimizing operational costs.
A computational model of the processes involved in multispectral remote sensing and data classification is developed as a tool for designing smart sensors which can process, edit, and classify the data that they acquire. An evaluation of sensor system performance and design tradeoffs involves classification rates and errors as a function of number and location of spectral channels, radiometric sensitivity and calibration accuracy, target discrimination assignments, and accuracy and frequency of compensation for imaging conditions. This model provides a link between the radiometric and statistical properties of the signals to be classified and the performance characteristics of electro-optical sensors and data processing devices. Preliminary computational results are presented which illustrate the editing performance of several remote sensing approaches.
The goal was the design and implementation of software to be used in the conceptual design of aerospace vehicles. Several packages and design studies were completed, including two software tools currently used in the conceptual level design of aerospace vehicles. These tools are the Solid Modeling Aerospace Research Tool (SMART) and the Environment for Software Integration and Execution (EASIE). SMART provides conceptual designers with a rapid prototyping capability and additionally provides initial mass property analysis. EASIE provides a set of interactive utilities that simplify the task of building and executing computer aided design systems consisting of diverse, stand alone analysis codes that result in the streamlining of the exchange of data between programs, reducing errors and improving efficiency.
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Buildings, as major energy consumers, can provide great untapped demand response (DR) resources for grid services. However, their participation remains low in real-life. One major impediment for popularizing DR in buildings is the lack of cost-effective automation systems that can be widely adopted. Existing optimization-based smart building control algorithms suffer from high costs on both building-specific modeling and on-demand computing resources. To tackle these issues, this paper proposes a cost-effective edge-cloud integrated solution using reinforcement learning (RL). Beside RL’s ability to solve sequential optimal decision-making problems, its adaptability to easy-to-obtain building models and the off-line learning feature are likely to reduce the controller’s implementation cost. Using a surrogate building model learned automatically from building operation data, an RL agent learns an optimal control policy on cloud infrastructure, and the policy is then distributed to edge devices for execution. Simulation results demonstrate the control efficacy and the learning efficiency in buildings of different sizes. A preliminary cost analysis on a 4-zone commercial building shows the annual cost for optimal policy training is only 2.25% of the DR incentive received. Results of this study show a possible approach with higher return on investment for buildings to participate in DR programs.
The goal of the Scalable Thin Light-Emitting Diode (LED) Light Sheet Platform project is to derisk the manufacturing scalability for a high chip count heterogeneous smart lighting platform, with the potential to enable significant energy savings through dynamic directional light control and custom. Specifically, the project derisks the scalability of a disruptive new computer controlled microassembly fabrication process SRI International is developing, to address fundamental cost barriers to mass production of high chip count systems. This is key for enabling mass adoption and thus maximum societal energy savings impact. The LED light sheet technology is a smart illumination platform that can be applied to lighting, signage, and display. It has features and a form factor similar to bendable or conformal OLED light sheets but uses more efficient LEDs with a remote phosphor layer that is very close to the LED to deliver a luminous efficacy that exceeds 125 lumen/Watt and enable > 50% Lighting Application Efficiency (LAE) energy savings. During Budget Period 1 (BP1), all of the BP1 milestones were successfully completed: (M2.0.1) Design demonstrator details that will meet the final project goals, (M6.1.1) Show lighting output model can predict illuminance, spatial, spectral distribution for specific light-sheet designs and use case, (M3.2.1) Automated loading supports 200 chip arrays, and (M3.3.1) Finish first interconnect process run for 200 chip array. The BP1 Go/No-Go Decision Point (G/NG 1) 200 chip demonstrator sample was in the process of final assembly and test at the end of BP1 on December 31, 2023. The objective was successfully achieved on January 16, 2024, when a wired 200-chip sample underwent confirmation testing that demonstrated a 93.75% first pass electrical yield that successfully exceeded the 75% first-pass electrical yield BP1 G/NG requirement. In addition, all 93.75% of the sample devices lit up, further demonstrating the ability to assemble and transfer small LED chips without damaging their functionality.
With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.
Typically, thousands of computationally expensive micro-scale simulations of brittle crack propagation are needed to upscale lower length scale phenomena to the macro-continuum scale. Running such a large number of crack propagation simulations presents a significant computational challenge, making reduced-order models (ROMs) attractive for this task. Here, the ultimate goal of this research is to develop ROMs that have sufficient accuracy and low computational cost so that these upscaling simulations can be readily performed. However, constructing ROMs for these complex simulations presents its own challenge. Here, we present and compare four different approaches for reduced-order modeling of brittle crack propagation in geomaterials. These methods rely on machine learning (ML) and graph-theoretic algorithms to approximate key aspects of the brittle crack problem. These methods also incorporate different physics-based assumptions in order to reduce the training requirements while maintaining accurate physics as much as possible. Results from the ROMs are directly compared against a high-fidelity model of brittle crack propagation. Further, the strengths and weaknesses of the ROMs are discussed, and we conclude that combining smart physics-informed feature engineering with highly trainable ML models provides the best performance. The ROMs considered here have computational costs that are orders-of-magnitude less than the cost associated with high-fidelity physical models while maintaining good accuracy.
The integration of distributed energy resources (DERs), such as solar photovoltaic systems, as well as other synergistic assets, including electric vehicles, energy storage, and smart appliances, in electric power systems has been dramatically increasing in the past few years. These assets have the capability to provide much-needed flexibility to electric power systems for improved grid reliability, resilience, and economic efficiency; however, most of these resources are located behind the meter (BTM) on customer premises, and their flexibility is not fully used in current grid operations. Grid-edge computing plays an important role in unlocking the great benefits and potential that BTM resources could provide to electric power systems by enhancing visibility and controllability at the grid edge.
A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..