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At least 235 records · Page 13

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NASA NTRS2001

MEMS Memory Elements

This paper presents a design example that illustrates the potential of microelectromechanical systems (MEMS) to perform the mechanical positioning required for addressing stored data and to enable an entirely new mechanism for reading and writing magnetic data. Specifically, MEMS sensors and actuators can be used to achieve active servo control of the separation between magnetic probe tips and a media surface with sub-nanometer accuracy. This allows mechanical position to be used to selectively write magnetic marks in a continuous thin-film magnetic media. In addition, MEMS sensors can be used to measure the separation between a magnetic probe tip and the media with a noise floor of roughly 22 picometers, allowing them to be used as position sensors in a magnetic force microscope (MFM) style data detection system.

Carley, L. Richard↗

NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗

NASA NTRS1997

Application-Controlled Demand Paging for Out-of-Core Visualization

In the area of scientific visualization, input data sets are often very large. In visualization of Computational Fluid Dynamics (CFD) in particular, input data sets today can surpass 100 Gbytes, and are expected to scale with the ability of supercomputers to generate them. Some visualization tools already partition large data sets into segments, and load appropriate segments as they are needed. However, this does not remove the problem for two reasons: 1) there are data sets for which even the individual segments are too large for the largest graphics workstations, 2) many practitioners do not have access to workstations with the memory capacity required to load even a segment, especially since the state-of-the-art visualization tools tend to be developed by researchers with much more powerful machines. When the size of the data that must be accessed is larger than the size of memory, some form of virtual memory is simply required. This may be by segmentation, paging, or by paged segments. In this paper we demonstrate that complete reliance on operating system virtual memory for out-of-core visualization leads to poor performance. We then describe a paged segment system that we have implemented, and explore the principles of memory management that can be employed by the application for out-of-core visualization. We show that application control over some of these can significantly improve performance. We show that sparse traversal can be exploited by loading only those data actually required. We show also that application control over data loading can be exploited by 1) loading data from alternative storage format (in particular 3-dimensional data stored in sub-cubes), 2) controlling the page size. Both of these techniques effectively reduce the total memory required by visualization at run-time. We also describe experiments we have done on remote out-of-core visualization (when pages are read by demand from remote disk) whose results are promising.

Cox, Michael↗

NASA NTRS1974

Quasi-perfect FIFO: Synchronous or asynchronous with application in controller design for the UNICON laser memory

The first-in-first-out memory buffer (FIFO), is an elastic digital memory whose main application is in data buffering between devices operating at different rates. Data written into the top is moved autonomously down toward the bottom of the FIFO to the lowest unoccupied location, and data read from the bottom of the FIFO will cause data from the top to move autonomously down toward the bottom. The FIFO is available in MOS LSI asynchronous form with data rate in the 1 MHz region. The FIFO described yields a simple high-speed iterative implementation, either synchronous of asynchronous. Because of this simple iterative structure, the FIFO is expandable in both number of words and bits per word, and it is attractive from the viewpoint of integrated-circuit production. For the synchronous FIFO, a model was built and successfully used in the controller for the UNICON laser memory. For the asynchronous FIFO, a model was built and also successfully used in a high-performance magnetic tape controller.

Lim, R. S.↗

NASA NTRS2017

How Much is Remembered as a Function of Presentation Modality?

According to a widespread claim often used for teaching recommendations, students remember 10 percent of what they read, 20 percent of what they hear, 30 percent of what they see, and 50 percent of what they see and hear. Clearly, the percentages cannot be correct, and there is no empirical evidence even for the ordering. To investigate the ordering, we used a laboratory paradigm that has already revealed some findings regarding the ordering of modalities for remembering information. In this paradigm, subjects are given messages instructing them to move in a grid of four stacked matrices by clicking a computer mouse. The current experiment compared 3 modalities presented either once, see (visual arrows), hear (auditory words), read (visual words); twice in succession, see see, hear hear, read read; or in two different successive modalities, see hear, hear see, see read, read see, hear read, read hear. We found better performance for messages presented twice than for those presented once, regardless of modality. For the twice-presented messages performance varied as a function of the second modality, with best performance for see and worst for read.

information↗

NASA NTRS1985

Six micrometer period wide-gap permalloy magnetic bubble devices

This report describes the progress made toward the goal of developing a 1 Mbit bubble memory chip, based on a 6 micron period wide-gap permalloy technology. Characterization of the functions showed that the guard-rail, generator, swap, write-line, read-line and after several revisions, the replicator and the expander-detector performed acceptably in preliminary testing. Several investigations were initiated to solve the problem of low minor loop yield. A dual-spacing process, which allows the minor loop propagation elements to be more tightly coupled to the garnet film was developed. Several new propagate structures, intended to be more tolerant of small defects were also conceived.

Chirovsky, L. M. F.↗

NASA NTRS1984

The role of knowledge structures in fault diagnosis

The use of human memory and knowledge structures to direct fault diagnosis performance was investigated. The performances of 20 pilots with instrument flight ratings were studied in a fault diagnosis task. The pilots were read a scenario which described flight conditions under which the symptoms which are indicative of a problem were detected. They were asked to think out loud as they requested and interpreted various pieces of information to diagnose the cause of the problem. Only 11 of the 20 pilots successfully diagnosed the problem. Pilot performance on this fault diagnosis task was modeled in the use of domain specific knowledge organized in a frame system. Eighteen frames, with a common structure, were necessary to account for the data from all twenty subjects.

Smith, P. J.↗

NASA NTRS2003

TID, SEE and radiation induced failures in advanced flash memories

We report on TID and SEE tests of multi-level and higher density flash memories. Stand-by currents and functionality tests were used to characterize the response of radiation-induced failures. The radiation-induced failures can be categorized as followings: SEU read errors during irradiation, stuck-bit read errors verified post-irradiation, write errors, erase failures, multiple upsets, and single-event latch up.

Scheick, Leif Z.↗

NASA NTRS1988

File-Format Program For Transferable Output ASCII Data

TOAD utilities machine-independent and require minimal central memory. Transferable Output ASCII Data (TOAD) file-format computer program facilitates transfer of data files from one computer installation to another. TOAD files preferred type and record length, easy to edit, read, and write on magnetic tape or transfer across communications networks. Applications programs write TOAD files directly and conform to all ANSI FORTRAN 77 standards.

Bingle, Bradford↗

NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗

NASA NTRS1988

Programmable Synaptic Arrays For Electronic Neural Networks

High resistances prevent hotspots in parallel input and output operation. Nonvolatile computer memory combines ultrahigh storage density with extremely-low power dissipation. Accommodates about 1 billion bits in square centimeter of surface area. Bit written with expenditure of less than 1 nanojoule of energy and read with even lower energy. Developed for parallel input and output operation.

Thakoor, Anilkumar P.↗

NASA NTRS2011

Experiment in Onboard Synthetic Aperture Radar Data Processing

Single event upsets (SEUs) are a threat to any computing system running on hardware that has not been physically radiation hardened. In addition to mandating the use of performance-limited, hardened heritage equipment, prior techniques for dealing with the SEU problem often involved hardware-based error detection and correction (EDAC). With limited computing resources, software- based EDAC, or any more elaborate recovery methods, were often not feasible. Synthetic aperture radars (SARs), when operated in the space environment, are interesting due to their relevance to NASAs objectives, but problematic in the sense of producing prodigious amounts of raw data. Prior implementations of the SAR data processing algorithm have been too slow, too computationally intensive, and require too much application memory for onboard execution to be a realistic option when using the type of heritage processing technology described above. This standard C-language implementation of SAR data processing is distributed over many cores of a Tilera Multicore Processor, and employs novel Radiation Hardening by Software (RHBS) techniques designed to protect the component processes (one per core) and their shared application memory from the sort of SEUs expected in the space environment. The source code includes calls to Tilera APIs, and a specialized Tilera compiler is required to produce a Tilera executable. The compiled application reads input data describing the position and orientation of a radar platform, as well as its radar-burst data, over time and writes out processed data in a form that is useful for analysis of the radar observations.

Holland, Matthew↗

NASA NTRS1985

Dynamic-RAM Data Storage Unit

Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.

Sturman, J. C.↗

NASA NTRS1981

A solid-state digital temperature recorder for space use

A solid-state, digital, temperature recorder has been developed for use in space experiments. The recorder is completely self-contained and includes a temperature sensor; all necessary electronics for signal conditioning, processing, storing, control and timing; and a battery power supply. No electrical interfacing with the particular spacecraft on which the unit is used is required. The recorder is small, light, and sturdy, and has no moving parts. It uses only biocompatible materials and has passed vibration and shock spaceflight qualification tests. The unit is capable of storing 2048, -10 to +45 C, 8-bit temperature measurements taken at intervals selectable by factors of 2 from 1.875 to 240 min; data can be retained for at least 6 months. The basic recorder can be simplified to accommodate a variety of applications by adding memory to allow more data to be recorded, by changing the front end to permit measurements other than temperature to be made, and by using different batteries to realize various operating periods. Stored flight data are read out from the recorder by means of a ground read-out unit.

Westbrook, R. M.↗

NASA NTRS2018

Climatespark: an In-Memory Distributed Computing Framework for Big Climate Data Analytics

The unprecedented growth of climate data creates new opportunities for climate studies, and yet big climate data pose a grand challenge to climatologists to efficiently manage and analyze big data. The complexity of climate data content and analytical algorithms increases the difficulty of implementing algorithms on high performance computing systems. This paper proposes an in-memory, distributed computing framework, ClimateSpark, to facilitate complex big data analytics and time-consuming computational tasks. Chunking data structure improves parallel I/O efficiency, while a spatiotemporal index is built for the chunks to avoid unnecessary data reading and preprocessing. An integrated, multi-dimensional, array-based data model (ClimateRDD) and ETL operations are developed to address big climate data variety by integrating the processing components of the climate data lifecycle. ClimateSpark utilizes Spark SQL and Apache Zeppelin to develop a web portal to facilitate the interaction among climatologists, climate data, analytic operations and computing resources (e.g., using SQL query and Scala/Python notebook). Experimental results show that ClimateSpark conducts different spatiotemporal data queries/analytics with high efficiency and data locality. ClimateSpark is easily adaptable to other big multiple- dimensional, array-based datasets in various geoscience domains.

Hu, Fei↗

NASA NTRS2013

Memory Circuit Fault Simulator

Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

Sheldon, Douglas J.↗

NASA NTRS1993

Three-Dimensional Magnetic-Bubble Memory System

Proposed magnetic-bubble memory system includes stack of two-dimensional memory modules. Design enables overall storage density of system to be greater than prior magnetic-bubble memories. Provides nonvolatile storage, with readout access times in millisecond range. Has partly parallel input/output configuration supporting high-performance computing. Also relatively invulnerable to damage by ionizing radiation. Binary data, as represented by direction of magnetization of magnetic bubbles, reads out via Faraday effect.

Katti, Romney R.↗

NASA NTRS1989

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Bartram, Peter N.↗