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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Memory-Related Frontal Brainwaves Predict Transition to Mild Cognitive Impairment in Healthy Older Individuals Five Years Before Diagnosis

Background: Early prognosis of high-risk older adults for amnestic mild cognitive impairment (aMCI), using noninvasive and sensitive neuromarkers, is key for early prevention of Alzheimer’s disease. We have developed individualized measures in electrophysiological brain signals during working memory that distinguish patients with aMCI from age-matched cognitively intact older individuals. Objective: Here we test longitudinally the prognosis of the baseline neuromarkers for aMCI risk. We hypothesized that the older individuals diagnosed with incident aMCI already have aMCI-like brain signatures years before diagnosis. Methods: Electroencephalogram (EEG) and memory performance were recorded during a working memory task at baseline. The individualized baseline neuromarkers, annual cognitive status, and longitudinal changes in memory recall scores up to 10 years were analyzed. Results: Seven of the 19 cognitively normal older adults were diagnosed with incident aMCI for a median 5.2 years later. The seven converters’ frontal brainwaves were statistically identical to those patients with diagnosed aMCI (n = 14) at baseline. Importantly, the converters’ baseline memory-related brainwaves (reduced mean frontal responses to memory targets) were significantly different from those who remained normal. Furthermore, differentiation pattern of left frontal memory-related responses (targets versus nontargets) was associated with an increased risk hazard of aMCI (HR = 1.47, 95% CI 1.03, 2.08). Conclusion: The memory-related neuromarkers detect MCI-like brain signatures about five years before diagnosis. The individualized frontal neuromarkers index increased MCI risk at baseline. These noninvasive neuromarkers during our Bluegrass memory task have great potential to be used repeatedly for individualized prognosis of MCI risk and progression before clinical diagnosis.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Benchmarking and Evaluating Unified Memory for OpenMP GPU Offloading

Here, the latest OpenMP standard offers automatic device offloading capabilities which facilitate GPU programming. Despite this, there remain many challenges. One of these is the unified memory feature introduced in recent GPUs. GPUs in current and future HPC systems have enhanced support for unified memory space. In such systems, CPU and GPU can access each other's memory transparently, that is, the data movement is managed automatically by the underlying system software and hardware. Memory over subscription is also possible in these systems. However, there is a significant lack of knowledge about how this mechanism will perform, and how programmers should use it. We have modified several benchmarks codes, in the Rodinia benchmark suite, to study the behavior of OpenMP accelerator extensions and have used them to explore the impact of unified memory in an OpenMP context. We moreover modified the open source LLVM compiler to allow OpenMP programs to exploit unified memory. The results of our evaluation reveal that, while the performance of unified memory is comparable with that of normal GPU offloading for benchmarks with little data reuse, it suffers from significant overhead when GPU memory is over subcribed for benchmarks with large amount of data reuse. Based on these results, we provide several guidelines for programmers to achieve better performance with unified memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2012

NVMalloc: Exposing an Aggregate SSD Store as a Memory Partition in Extreme-Scale Machines

DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-petaflop and exaflop machines, the memory pressure is likely to be so severe that we need to rethink our memory usage models. Fortunately, the advent of non-volatile memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach for exploiting NVM as a secondary memory partition so that applications can explicitly allocate and manipulate memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the memory mapped I/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall memory capacity available. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical memory in a cost-effective manner. It can bring more performance/efficiency gain with increased computation time between NVM memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.

Computer Science↗
DOE OSTI2019

Umpire: Application-Focused Management and Coordination of Complex Hierarchical Memory

Advanced architectures like Sierra provide a wide range of memory resources that must often be carefully controlled by the user. These resources have varying capacities, access timing rules, and visibility to different compute resources. Applications must intelligently allocate data in these spaces, and depending on the total amount of memory required, applications may also be forced to move data between different parts of the memory hierarchy. Finally, applications using multiple packages must coordinate effectively to ensure that each package can use the memory resources it needs. To address these challenges, we present Umpire, an application-oriented library for managing memory resources. Specifically, Umpire provides support for querying memory resources, provisioning and allocating memory, and memory introspection. It allows computer scientists and computational physicists to efficiently program the memory hierarchies of current and future high-performance computing architectures, without tying their application to specific hardware or software. In this paper, we describe the design and implementation of Umpire and present case studies from the integration of Umpire into applications that are currently running on Sierra.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Improving Memory Error Handling Using Linux

As supercomputers continue to get faster and more powerful in the future, they will also have more nodes. If nothing is done, then the amount of memory in supercomputer clusters will soon grow large enough that memory failures will be unmanageable to deal with by manually replacing memory DIMMs. "Improving Memory Error Handling Using Linux" is a process oriented method to solve this problem by using the Linux kernel to disable (offline) faulty memory pages containing bad addresses, preventing them from being used again by a process. The process of offlining memory pages simplifies error handling and results in reducing both hardware and manpower costs required to run Los Alamos National Laboratory (LANL) clusters. This process will be necessary for the future of supercomputing to allow the development of exascale computers. It will not be feasible without memory error handling to manually replace the number of DIMMs that will fail daily on a machine consisting of 32-128 petabytes of memory. Testing reveals the process of offlining memory pages works and is relatively simple to use. As more and more testing is conducted, the entire process will be automated within the high-performance computing (HPC) monitoring software, Zenoss, at LANL.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Memory Optimization for Phase-field Simulations

Phase-field simulations are computationally and memory intensive applications. Many of the phase-field simulations being conducted in support of NEAMS were not capable of running on “normal clusters” with 2-4GB of RAM per core, and instead required specialized “big-memory” clusters with 64GB per core. To address this issue, the MOOSE team developed a new Python-based utility called MemoryLogger, and applied it to locate, diagnose, and eradicate memory bottlenecks within the MOOSE framework. MemoryLogger allows for a better understanding of the memory usage of an application being run in parallel across a cluster. Memory usage information is captured for every individual process in a parallel job, and communicated to the head node of the cluster. Console text output from the application itself is automatically matched with this memory usage information to produce a detailed picture of memory usage over time, making it straightforward to identify the subroutines which contribute most to the application’s peak memory usage. The information produced by the MemoryLogger quickly and effectively narrows the search for memory optimizations to the most data-intensive parts of the simulation.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2014

Energy-aware Thread and Data Management in Heterogeneous Multi-core, Multi-memory Systems

By 2004, microprocessor design focused on multicore scaling—increasing the number of cores per die in each generation—as the primary strategy for improving performance. These multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing volume of hardware resources and system complexity caused by heterogeneity, future systems will require intelligent ways to manage hardware resources. Early research to improve performance and energy efficiency on heterogeneous, multi-core, multi-memory systems focused on tuning a single primitive or at best a few primitives in the systems. The key limitation of past efforts is their lack of a holistic approach to resource management that balances the tradeoff between performance and energy consumption. In addition, the shift from simple, homogeneous systems to these heterogeneous, multicore, multi-memory systems requires in-depth understanding of efficient resource management for scalable execution, including new models that capture the interchange between performance and energy, smarter resource management strategies, and novel low-level performance/energy tuning primitives and runtime systems. Tuning an application to control available resources efficiently has become a daunting challenge; managing resources in automation is still a dark art since the tradeoffs among programming, energy, and performance remain insufficiently understood. In this dissertation, I have developed theories, models, and resource management techniques to enable energy-efficient execution of parallel applications through thread and data management in these heterogeneous multi-core, multi-memory systems. I study the effect of dynamic concurrent throttling on the performance and energy of multi-core, non-uniform memory access (NUMA) systems. I use critical path analysis to quantify memory contention in the NUMA memory system and determine thread mappings. In addition, I implement a runtime system that combines concurrent throttling and a novel thread mapping algorithm to manage thread resources and improve energy efficient execution in multi-core, NUMA systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Sparse Matrix-Matrix Multiplication on Multilevel Memory Architectures: Algorithms and Experiments

Architectures with multiple classes of memory media are becoming a common part of mainstream supercomputer deployments. So called multi-level memories offer differing characteristics for each memory component including variation in bandwidth, latency and capacity. This paper investigates the performance of sparse matrix multiplication kernels on two leading highperformance computing architectures — Intel's Knights Landing processor and NVIDIA's Pascal GPU. We describe a data placement method and a chunking-based algorithm for our kernels that exploits the existence of the multiple memory spaces in each hardware platform. We evaluate the performance of these methods w.r.t. standard algorithms using the auto-caching mechanisms Our results show that standard algorithms that exploit cache reuse performed as well as multi-memory-aware algorithms for architectures such as Ki\iLs where the memory subsystems have similar latencies. However, for architectures such as GPUS where memory subsystems differ significantly in both bandwidth and latency, multi-memory-aware methods are crucial for good performance. In addition, our new approaches permit the user to run problems that require larger capacities than the fastest memory of each compute node without depending on the software-managed cache mechanisms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Gravitational-wave and Gravitational-wave Memory Signatures of Core-collapse Supernovae

Abstract In this paper, we calculate the energy, signal-to-noise ratio (SNR), detection range, and angular anisotropy of the matter, matter memory, and neutrino memory gravitational-wave (GW) signatures of 21 three-dimensional initially nonrotating core-collapse supernova (CCSN) models carried to late times. We find that inferred energy, SNR, and detection range are angle-dependent quantities, and that the spread of possible energy, signal to noise, and detection ranges across all viewing angles generally increases with progenitor mass. When examining the low-frequency matter memory and neutrino memory components of the signal, we find that the neutrino memory is the most detectable component of a CCSN GW signal, and that DECIGO is best equipped to detect both matter memory and neutrino memory. Moreover, we find that the polarization angle between the h + and h × strains serves as a unique identifier of matter and neutrino memory. Finally, we develop a Galactic density- and stellar mass-weighted formalism to calculate the rate at which we can expect to detect CCSN GW signals with the Advanced Laser Interferometer Gravitational-Wave Observatory (aLIGO). When considering only the matter component of the signal, the aLIGO detection rate is around 65% of the total Galactic supernova rate, but increases to 90% when incorporating the neutrino memory component. We find that all future detectors (Einstein Telescope, Cosmic Explorer, DECIGO) will be able to detect CCSN GW signals from the entire Galaxy, and for the higher-mass progenitors even into the Local Group of galaxies.

Choi, Lyla (ORCID:0000000153860133)↗
NASA NTRS1975

System applications of the fault tolerant memory

Conventional memory technologies currently employed in aerospace applications contribute at least fifty percent to system unreliability (where the system includes CPU, I/O and memory). A fault tolerant memory performs both error correction and memory replacement at the bit plane level. To determine the effects of system design of using a fault tolerant memory in space applications, analysis was performed to determine tradeable hardware configurations that meet the reliability goals of each program. The candidate configurations, which included redundant elements of the computer system with both conventional and fault tolerant memories, were then traded in terms of selection criteria of cost, weight, volume, and power. These trade studies demonstrated that a fault tolerant memory provided significant advantages in terms of cost, weight, and volume. The memory selected for this analysis was a recently developed five fault tolerant memory.

Murphy, L. J.↗
NASA NTRS1982

A generalized memory test algorithm

A general algorithm for testing digital computer memory is presented. The test checks that (1) every bit can be cleared and set in each memory work, and (2) bits are not erroneously cleared and/or set elsewhere in memory at the same time. The algorithm can be applied to any size memory block and any size memory word. It is concise and efficient, requiring the very few cycles through memory. For example, a test of 16-bit-word-size memory requries only 384 cycles through memory. Approximately 15 seconds were required to test a 32K block of such memory, using a microcomputer having a cycle time of 133 nanoseconds.

Milner, E. J.↗
NASA NTRS1984

Automatic multi-banking of memory for microprocessors

A microprocessor system is provided with added memories to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch.

Wiker, G. A.↗
NASA NTRS1987

The capacity of the Hopfield associative memory

Techniques from coding theory are applied to study rigorously the capacity of the Hopfield associative memory. Such a memory stores n-tuple of + or - 1s. The components change depending on a hard-limited version of linear functions of all other components. With symmetric connections between components, a stable state is ultimately reached. By building up the connection matrix as a sum-of-outer products of m fundamental memories, it may be possible to recover a certain one of the m memories by using an initial n-tuple probe vector less than a Hamming distance n/2 away from the fundamental memory. If m fundamental memories are chosen at random, the maximum asymptotic value of m in order that most of the m original memories are exactly recoverable is n/(2 log n). With the added restriction that every one of the m fundamental memories be recoverable exactly, m can be no more than n/(4 log n) asymptotically as n approaches infinity. Extensions are also considered, in particular to capacity under quantization of the outer-product connection matrix. This quantized memory-capacity problem is closely related to the capacity of the quantized Gaussian channel.

Mceliece, Robert J.↗
NASA NTRS1990

Sparse distributed memory overview

The Sparse Distributed Memory (SDM) project is investigating the theory and applications of massively parallel computing architecture, called sparse distributed memory, that will support the storage and retrieval of sensory and motor patterns characteristic of autonomous systems. The immediate objectives of the project are centered in studies of the memory itself and in the use of the memory to solve problems in speech, vision, and robotics. Investigation of methods for encoding sensory data is an important part of the research. Examples of NASA missions that may benefit from this work are Space Station, planetary rovers, and solar exploration. Sparse distributed memory offers promising technology for systems that must learn through experience and be capable of adapting to new circumstances, and for operating any large complex system requiring automatic monitoring and control. Sparse distributed memory is a massively parallel architecture motivated by efforts to understand how the human brain works. Sparse distributed memory is an associative memory, able to retrieve information from cues that only partially match patterns stored in the memory. It is able to store long temporal sequences derived from the behavior of a complex system, such as progressive records of the system's sensory data and correlated records of the system's motor controls.

Raugh, Mike↗
NASA NTRS1993

Magellan spacecraft and memory state tracking: Lessons learned, future thoughts

Numerous studies have been dedicated to improving the two main elements of Spacecraft Mission Operations: Command and Telemetry. As a result, not much attention has been given to other tasks that can become tedious, repetitive, and error prone. One such task is Spacecraft and Memory State Tracking, the process by which the status of critical spacecraft components, parameters, and the contents of on-board memory are managed on the ground to maintain knowledge of spacecraft and memory states for future testing, anomaly investigation, and on-board memory reconstruction. The task of Spacecraft and Memory State Tracking has traditionally been a manual task allocated to Mission Operations Procedures. During nominal Mission Operations this job is tedious and error prone. Because the task is not complex and can be accomplished manually, the worth of a sophisticated software tool is often questioned. However, in the event of an anomaly which alters spacecraft components autonomously or a memory anomaly such as a corrupt memory or flight software error, an accurate ground image that can be reconstructed quickly is a priceless commodity. This study explores the process of Spacecraft and Memory State Tracking used by the Magellan Spacecraft Team highlighting its strengths as well as identifying lessons learned during the primary and extended missions, two memory anomalies, and other hardships encountered due to incomplete knowledge of spacecraft states. Ideas for future state tracking tools that require minimal user interaction and are integrated into the Ground Data System will also be discussed.

Bucher, Allen W.↗
NASA NTRS1993

A petabyte size electronic library using the N-Gram memory engine

A model library containing petabytes of data is proposed by Triada, Ltd., Ann Arbor, Michigan. The library uses the newly patented N-Gram Memory Engine (Neurex), for storage, compression, and retrieval. Neurex splits data into two parts: a hierarchical network of associative memories that store 'information' from data and a permutation operator that preserves sequence. Neurex is expected to offer four advantages in mass storage systems. Neurex representations are dense, fully reversible, hence less expensive to store. Neurex becomes exponentially more stable with increasing data flow; thus its contents and the inverting algorithm may be mass produced for low cost distribution. Only a small permutation operator would be recalled from the library to recover data. Neurex may be enhanced to recall patterns using a partial pattern. Neurex nodes are measures of their pattern. Researchers might use nodes in statistical models to avoid costly sorting and counting procedures. Neurex subsumes a theory of learning and memory that the author believes extends information theory. Its first axiom is a symmetry principle: learning creates memory and memory evidences learning. The theory treats an information store that evolves from a null state to stationarity. A Neurex extracts information data without a priori knowledge; i.e., unlike neural networks, neither feedback nor training is required. The model consists of an energetically conservative field of uniformly distributed events with variable spatial and temporal scale, and an observer walking randomly through this field. A bank of band limited transducers (an 'eye'), each transducer in a bank being tuned to a sub-band, outputs signals upon registering events. Output signals are 'observed' by another transducer bank (a mid-brain), except the band limit of the second bank is narrower than the band limit of the first bank. The banks are arrayed as n 'levels' or 'time domains, td.' The banks are the hierarchical network (a cortex) and transducers are (associative) memories. A model Neurex was built and studied. Data were 50 MB to 10 GB samples of text, data base, and images: black/white, grey scale, and high resolution in several spectral bands. Memories at td, S(m(sub td)), were plotted against outputs of memories at td-1. S(m(sub td)) was Boltzman distributed, and memory frequencies exhibited self-organized criticality (SOC); i.e., 'l/f(sup beta)' after long exposures to data. Whereas output signals from level n may be encoded with B(sub output) = O(-log(2)f(sup beta)) bits, and input data encoded with B(sub input) = O((S(td)/S(td-1))(sup n)), B(sup output)/B(sub input) is much less than 1 always, the Neurex determines a canonical code for data and it is a lossless data compressor. Further tests are underway to confirm these results with more data types and larger samples.

Bugajski, Joseph M.↗
NASA NTRS2001

Future Development of Dense Ferroelectric Memories for Space Applications

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Philpy, Stephen C.↗