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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Mueller, Carl↗
NASA NTRS2018

Solid State Ephemeral Electric Potential and Electric Field Sensor

Systems, methods, and devices of the various embodiments provide a field effect transistor (FET) that controls equilibrium by reversing the effects of leakage currents affecting the gate response of the FET by using an equilibrium pump electrode. The equilibrium reversing gate FETs (ergFETs) of the various embodiments, may include an equilibrium pump electrode located within a non-conducting gap. The ergFETs of the various embodiments may provide solid state ephemeral electric potential and electric field sensor systems and methods for measuring ephemeral electric potentials and electric fields.

Generazio, Edward R.↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
NASA NTRS1986

Noise parameters and light sensitivity of low-noise high-electron-mobility transistors at 300 and 12.5 K

The four noise parameters of cryogenically cooled HEMTs have been investigated. Two different HEMT structures, with and without a spacer layer, were tested. The noise parameters of both structures were similar at room temperature, while they were dramatically different at cryogenic temperatures. The minimum noise temperatures measured at 8.4 GHz were 75 + or 5 K at room temperature and 8.5 + or - 1.5 K at the temperature of 12.5 K. The cryogenic performance is the best ever observed for field-effect transistors.

Pospieszalski, Marian W.↗
NASA NTRS1981

A gallium phosphide high-temperature bipolar junction transistor

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Zipperian, T. E.↗
NASA NTRS1992

Noise-optimal control of HEMT LNA's for compensation of temperature deviations

Noise-optimal control of high-electron mobility transistor low noise amplifier (HEMT LNA) bias voltage and current values was achieved at room temperature. The performance metric maximized was the amplifier gain divided by the amplifier input noise temperature, G/T(sub e). Additionally, the feasibility of automating the initial determination of bias settings was demonstrated in the laboratory. Simulation models of an HEMT were developed from available measurement data, installed on a Sun SPARC 1 workstation, and used in investigating several optimization algorithms. Simple tracking-type algorithms, which follow changes in optimum settings if started at or near the global optimum point, produced the best performance. Implementation of the optimization algorithms was performed using a three-stage Field Effect Transistor (FET) LNA and an existing test apparatus. Software was written to control the bias settings of the first stage of the LNA and to perform noise and gain measurements by using the test apparatus. The optimization control was then integrated with existing test software to create a master test and optimization program for test apparatus use.

Maccarley, C.↗
NASA NTRS2005

High-Efficiency Microwave Power Amplifier

A high-efficiency power amplifier that operates in the S band (frequencies of the order of a few gigahertz) utilizes transistors operating under class-D bias and excitation conditions. Class-D operation has been utilized at lower frequencies, but, until now, has not been exploited in the S band. Nominally, in class D operation, a transistor is switched rapidly between "on" and "off" states so that at any given instant, it sustains either high current or high voltage, but not both at the same time. In the ideal case of zero "on" resistance, infinite "off" resistance, zero inductance and capacitance, and perfect switching, the output signal would be a perfect square wave. Relative to the traditional classes A, B, and C of amplifier operation, class D offers the potential to achieve greater power efficiency. In addition, relative to class-A amplifiers, class-D amplifiers are less likely to go into oscillation. In order to design this amplifier, it was necessary to derive mathematical models of microwave power transistors for incorporation into a larger mathematical model for computational simulation of the operation of a class-D microwave amplifier. The design incorporates state-of-the-art switching techniques applicable only in the microwave frequency range. Another major novel feature is a transmission-line power splitter/combiner designed with the help of phasing techniques to enable an approximation of a square-wave signal (which is inherently a wideband signal) to propagate through what would, if designed in a more traditional manner, behave as a more severely band-limited device (see figure). The amplifier includes an input, a driver, and a final stage. Each stage contains a pair of GaAs-based field-effect transistors biased in class D. The input signal can range from -10 to +10 dBm into a 50-ohm load. The table summarizes the performances of the three stages

Sims, Williams H.↗
NASA NTRS2011

Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR susceptibility is explored. SEGR evaluation of gamma-irradiated power MOSFETs suggests a non-significant SEGR susceptibility enhancement due to accumulated dose from gamma rays. During SEGR testing, an unexpected enhanced dose effect from heavy-ion irradiation was detected. We demonstrate that this effect could be due to direct ionization by two or more ions at the same channel location. The probability on-orbit for such an occurrence is near-zero given the low heavy-ion fluence over a typical mission lifetime, and did not affect SEGR susceptibility. The results of this work can be used to bound the risk of SEGR in power MOSFETs considered for insertion into spacecraft and instruments.

Lauenstein, Jean-Marie↗
NASA NTRS2010

Fully Printed High-Frequency Phased-Array Antenna on Flexible Substrate

To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.

Chen, Yihong↗
NASA NTRS1964

Put FETs to Work in Electrometers

Field-effect transistors, with their high impedance and low noise, can effectively measure very low currents. To bring the FET up to electrometer standards (so that it can measure currents of, say, 10 (sup -13) amp) the designer must know where the noise is and what to do about it.

ELECTROMETER↗
NASA NTRS1966

MOSFET analog memory circuit achieves long duration signal storage

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Source record↗
NASA NTRS1967

An efficient, temperature-compensated subcarrier oscillator

Telemetry subcarrier oscillator has temperature stability, consumes a minimum of power, and has a high input impedance. Its output frequency is a linear function of the magnitude of an input signal. A circuit using an input buffer with a field effect transistor serves as the temperature-compensating element.

Lawrence, E. D.↗
NASA NTRS1967

Improved circuit for measuring capacitive and inductive reactances

Amplifier circuit measures very small changes of capacitive or inductive reactance, such as produced by a variable capacitance or a variable inductance displacement transducer. The circuit employs reactance-sensing oscillators in which field effect transistors serve as the active elements.

Dalins, I.↗
NASA NTRS1968

Engineering Mechanics Division

Screening methods for metal oxide semiconductor field effect transistors and resistors, impact survival testing of spacecraft electronic parts, and parachute jettisoning from planetary capsules

Source record↗