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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1974

A stable, linear frequency-modulated oscillator, part 1

The development of a push-pull frequency-modulated oscillator employing field-effect transistors is described. The advantages of field-effect transistors for use in a frequency-stable oscillator are presented. Linearization of the frequency deviation was accomplished by utilizing the square-law characteristic of an FET used as a modulating amplifier. The push-pull oscillator model produced a linear frequency deviation of more than 10 MHz at a center frequency of approximately 100 MHz. Output power is within 0.6 db of a nominal +8.5 dBm over the desired frequency range, and the modulation bandwidth is dc to 10 MHz. Frequency variation with temperature after compensation with a negative-temperature-coefficient capacitor is within + or - 0.05% from 0 to 60 C.

Honnell, M. A.↗
NASA NTRS1989

A digitally controlled system for effecting and presenting a selected electrical resistance

A digitally controlled resistance generator is described, in which resistors having values selected according to an expression 2(sup N-1)(R), where N is equal to the number of terms in the expression, and R is equal to the lowest value of resistance, are electrically inserted into a resistive circuit in accordance with a parallel binary signal provided by an analog-to-digital converter or a programmable computer. This binary signal is coupled via optical isolators which, when activated by a logical 1, provides a negative potential to some or all of the gate inputs of the normally on field effect transistors which, when on, shorts out the associated resistor. This applied negative potential turns the field effect transistors off and electrically inserts the resistor coupled between the source terminal and the drain terminal of that field effect transistor into the resistive circuit between the terminals.

Fletcher, James C.↗
DOE OSTI2021

Heterometallic Actinide‐Containing Photoresponsive Metal‐Organic Frameworks: Dynamic and Static Tuning of Electronic Properties

Abstract Acquiring fundamental knowledge of properties of actinide‐based materials is a necessary step to create new possibilities for addressing the current challenges in the nuclear energy and nuclear waste sectors. In this report, we established a photophysics–electronics correlation for actinide‐containing metal‐organic frameworks (An‐MOFs) as a function of excitation wavelength, for the first time. A stepwise approach for dynamically modulating electronic properties was applied for the first time towards actinide‐based heterometallic MOFs through integration of photochromic linkers. Optical cycling, modeling of density of states near the Fermi edge, conductivity measurements, and photoisomerization kinetics were employed to shed light on the process of tailoring optoelectronic properties of An‐MOFs. Furthermore, the first photochromic MOF‐based field‐effect transistor, in which the field‐effect response could be changed through light exposure, was constructed. As a demonstration, the change in current upon light exposure was sufficient to operate a two‐LED fail‐safe indicator circuit.

Martin, Corey R.↗
NASA NTRS1979

Solid-state X-band Combiner Study

The feasibility of developing solid-state amplifiers at 4 and 10 GHz for application in spacecraft altimeters was studied. Bipolar-transistor, field-effect-transistor, and Impatt-diode amplifier designs based on 1980 solid-state technology are investigated. Several output power levels of the pulsed, low-duty-factor amplifiers are considered at each frequency. Proposed transistor and diode amplifier designs are illustrated in block diagrams. Projections of size, weight, and primary power requirements are given for each design.

Pitzalis, O., Jr.↗
NASA NTRS1984

Energy-Saving Inverter

Commutation by field-effect transistor allows more efficient operation. High voltage field-effect transistor (FET) controls silicon controlled rectifiers (SCR's). Circuit requires only one capacitor and one inductor in commutation circuit: simpler, more efficient, and more economical than conventional inverters. Adaptable to dc-to-dc converters.

Rippel, W. E.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
DOE OSTI2022

Manipulating high-temperature superconductivity by oxygen doping in Bi2Sr2CaCu2O8+δ thin flakes

Abstract Harnessing the fascinating properties of correlated oxides requires precise control of their carrier density. Compared to other methods, oxygen doping provides an effective and more direct way to tune the electronic properties of correlated oxides. Although several approaches, such as thermal annealing and oxygen migration, have been introduced to change the oxygen content, a continuous and reversible solution that can be integrated with modern electronic technology is much in demand. Here, we report a novel ionic field-effect transistor using solid Gd-doped CeO2 as the gate dielectric, which shows a remarkable carrier-density-tuning ability via electric-field-controlled oxygen concentration at room temperature. In Bi2Sr2CaCu2O8+δ (Bi-2212) thin flakes, we achieve a reversible superconductor–insulator transition by driving oxygen ions in and out of the samples with electric fields, and map out the phase diagram all the way from the insulating regime to the over-doped superconducting regime by continuously changing the oxygen doping level. Scaling analysis indicates that the reversible superconductor–insulator transition for the Bi-2212 thin flakes follows the theoretical description of a two-dimensional quantum phase transition. Our work provides a route for realizing electric-field control of phase transition in correlated oxides. Moreover, the configuration of this type of transistor makes heterostructure/interface engineering possible, thus having the potential to serve as the next-generation all-solid-state field-effect transistor.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

Selective area doping of GaN toward high-power applications

Abstract Selective area doping in GaN, especially p-type, is a critical and inevitable building block for the realization of advanced device structures for high-power applications, including, but not limited to, current-aperture vertical electron transistors, junction termination extensions, junction barrier Schottky diodes, junction field-effect transistors (JFETs), vertical-channel JFETs, U-shaped metal–oxide–semiconductor field-effect transistors (U-MOSFETs), and Fin MOSFETs. This paper reviews and summarizes some of the recent advances in the fields of selective area etching and regrowth, ion implantation, and polarity-dependent doping that may lead to the practical realization of GaN-based power devices.

Physics↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
DOE OSTI2025

Next-generation tunnel FETs: exploring material perspectives and areal tunneling configurations

The end of Dennard scaling, which facilitated proportional increases in computing power without added energy costs until the mid-2000s, has underscored the urgent need for innovative semiconductor devices that can enhance energy efficiency. Tunnel field-effect transistors (TFETs) have emerged as promising candidates to surpass the energy efficiency of conventional metal oxide semiconductor field-effect transistors (MOSFETs). Unlike MOSFETs, which rely on thermionic emission to overcome the source-channel potential barrier, TFETs operate through quantum tunneling, potentially enabling sub-60 mV dec −1 subthreshold swing (SS) for low-voltage operation. However, lateral TFETs have faced challenges in achieving adequate on-state current (I ON ) and a broad SS operation window, limiting their practical utility. This review article advocates for areal TFETs, which utilize face-to-face tunnel junctions that ideally offer step-function current turn-on characteristics and allow I ON to scale with device area rather than width. We highlight recent advancements in integrating 2D materials into tunneling structures, which could facilitate efficient band-to-band tunneling through atomically thin layers, while addressing challenges of gate field screening. We then discuss the nearer-term prospects of epitaxial areal TFETs comprising III–V compound semiconductors and group-IV semiconductors based on recent experimental progress. The review examines both quantum mechanical and semiclassical modeling approaches for TFETs, including techniques to reduce the computational complexity. The article delves into ongoing challenges in material synthesis, interface engineering, device fabrication, and integration pathways, concluding with recommendations for future research directions to overcome the fundamental power density limitations of conventional transistor technology.

2D materials↗
DOE OSTI2020

Monolithically-integrated AC switch having JBSFETs therein with commonly-connected drain and cathode electrodes

A monolithically-integrated AC switch includes a semiconductor substrate having first and second insulated-gate field effect transistors therein, which contain first and second spaced-apart and independently-controllable source terminals extending adjacent a first surface of the semiconductor substrate, yet share a common drain electrode extending adjacent a second surface of the semiconductor substrate. According to some of these embodiments of the invention, the first and second insulated-gate field effect transistors include respective first and second independently-controllable gate electrodes, which extend adjacent the first surface. The first and second insulated-gate field effect transistors may be configured as first and second vertical power MOSFETs, respectively. The semiconductor substrate may also include at least one edge termination region therein, which extends between the first and second vertical power MOSFETs.

42 ENGINEERING↗
NASA NTRS1987

Electronic Power Switch for Fault-Tolerant Networks

Power field-effect transistors reduce energy waste and simplify interconnections. Current switch containing power field-effect transistor (PFET) placed in series with each load in fault-tolerant power-distribution system. If system includes several loads and supplies, switches placed in series with adjacent loads and supplies. System of switches protects against overloads and losses of individual power sources.

Volp, J.↗
NASA NTRS1984

Low noise tuned amplifier

A bandpass amplifier employing a field effect transistor amplifier first stage is described with a resistive load either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load of the field effect transistor.

Kleinberg, L. L.↗
DOE OSTI2021

Steep slope transistors with threshold switching devices

A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.

Huang, Xuanqi↗