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229 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

Context Cameras for the Orbiting Carbon Observatory 3 (OCO-3) Instrument

We have developed an adaptable camera platform that takes advantage of screened and qualified commercial off the shelf (COTS) components (CMOS sensor, rad-tolerant microcircuits, lenses) to significantly shorten development time of space-borne visible imaging systems while reducing the overall cost and risk of the development. This modular camera platform is implemented as a suite of two visible-light cameras for the Orbiting Carbon Observatory 3 (OCO-3) instrument at NASA’s Jet Propulsion Laboratory (JPL). The Internal Context Camera (ICC) and External Context Camera (ECC) provide contextual engineering imaging support for the calibration of the OCO-3 instrument, intended to significantly reduce the duration of the mission’s calibration campaign. The OCO-3 mission has taken advantage of the design and qualification work performed by JPL’s Mars 2020 Enhanced Engineering Camera (EECam) team in reusing the qualified COTS CMOS imaging sensor, proven electronic designs, and scalable field-programmable gate array (FPGA) firmware to meet OCO-3’s mission requirements and resource availability. We will be presenting the steps taken by JPL to design, build, and test the Context Cameras for the OCO-3 mission. We will highlight the design deviations from the Mars2020 EECams and discuss the methodology of tailoring the EECam design for the OCO-3 requirements. Camera imaging capabilities, including focal plane and optical performance, will be presented, as well as a summary of the calibration and environmental test results. Finally, we will discuss the potential for future applications for the Context Cameras.

Moore, Douglas↗
NASA NTRS2008

25th Space Simulation Conference. Environmental Testing: The Earth-Space Connection

Topics covered include: Methods of Helium Injection and Removal for Heat Transfer Augmentation; The ESA Large Space Simulator Mechanical Ground Support Equipment for Spacecraft Testing; Temperature Stability and Control Requirements for Thermal Vacuum/Thermal Balance Testing of the Aquarius Radiometer; The Liquid Nitrogen System for Chamber A: A Change from Original Forced Flow Design to a Natural Flow (Thermo Siphon) System; Return to Mercury: A Comparison of Solar Simulation and Flight Data for the MESSENGER Spacecraft; Floating Pressure Conversion and Equipment Upgrades of Two 3.5kw, 20k, Helium Refrigerators; Affect of Air Leakage into a Thermal-Vacuum Chamber on Helium Refrigeration Heat Load; Special ISO Class 6 Cleanroom for the Lunar Reconnaissance Orbiter (LRO) Project; A State-of-the-Art Contamination Effects Research and Test Facility Martian Dust Simulator; Cleanroom Design Practices and Their Influence on Particle Counts; Extra Terrestrial Environmental Chamber Design; Contamination Sources Effects Analysis (CSEA) - A Tool to Balance Cost/Schedule While Managing Facility Availability; SES and Acoustics at GSFC; HST Super Lightweight Interchangeable Carrier (SLIC) Static Test; Virtual Shaker Testing: Simulation Technology Improves Vibration Test Performance; Estimating Shock Spectra: Extensions beyond GEVS; Structural Dynamic Analysis of a Spacecraft Multi-DOF Shaker Table; Direct Field Acoustic Testing; Manufacture of Cryoshroud Surfaces for Space Simulation Chambers; The New LOTIS Test Facility; Thermal Vacuum Control Systems Options for Test Facilities; Extremely High Vacuum Chamber for Low Outgassing Processing at NASA Goddard; Precision Cleaning - Path to Premier; The New Anechoic Shielded Chambers Designed for Space and Commercial Applications at LIT; Extraction of Thermal Performance Values from Samples in the Lunar Dust Adhesion Bell Jar; Thermal (Silicon Diode) Data Acquisition System; Aquarius's Instrument Science Data System (ISDS) Automated to Acquire, Process, Trend Data and Produce Radiometric System Assessment Reports; Exhaustive Thresholds and Resistance Checkpoints; Reconfigurable HIL Testing of Earth Satellites; FPGA Control System for the Automated Test of MicroShutters; Ongoing Capabilities and Developments of Re-Entry Plasma Ground Tests at EADS-ASTRIUM; Operationally Responsive Space Standard Bus Battery Thermal Balance Testing and Heat Dissipation Analysis; Galileo - The Serial-Production AIT Challenge; The Space Systems Environmental Test Facility Database (SSETFD), Website Development Status; Simulated Reentry Heating by Torching; Micro-Vibration Measurements on Thermally Loaded Multi-Layer Insulation Samples in Vacuum; High Temperature Life Testing of 80Ni-20Cr Wire in a Simulated Mars Atmosphere for the Sample Analysis at Mars (SAM) Instrument Suit Gas Processing System (GPS) Carbon Dioxide Scrubber; The Planning and Implementation of Test Facility Improvements; and Development of a Silicon Carbide Molecular Beam Nozzle for Simulation Planetary Flybys and Low-Earth Orbit.

Packard, Edward↗
NASA NTRS2011

Peak Satellite-to-Earth Data Rates Derived From Measurements of a 20 Gbps Bread-Board Modem

A prototype data link using a Ka-band space qualified, high efficiency 200 W TWT amplifier and a bread-board modem emulator were created to explore the feasibility of very high speed communications in satellite-to-earth applications. Experiments were conducted using a DVB-S2-like waveform with modifications to support up to 20 Gbps through the addition of 128-Quadrature Amplitude Modulation (QAM). Limited by the bandwidth of the amplifier, a constant peak symbol rate of 3.2 Giga-symbols/sec was selected and the modulation order was varied to explore what peak data rate might be supported by an RF link through this amplifier. Using 128-QAM, an implementation loss of 3 dB was observed at 20 Gbps, and the loss decreased as data rate or bandwidth were reduced. Building on this measured data, realistic link budget calculations were completed. Low-Earth orbit (LEO) missions based on this TWTA with reasonable hardware assumptions and antenna sizing are found to be bandwidth-limited, rather than power-limited, making the spectral efficiency of 9/10-rate encoded 128-QAM very attractive. Assuming a bandwidth allocation of 1 GHz, these computations indicate that low-Earth orbit vehicles could achieve data rates up to 5 Gbps-an order of magnitude beyond the current state-of-practice, yet still within the processing power of a current FPGA-based software-defined modem. The measured performance results and a description of the experimental setup are presented to support these conclusions.

Landon, David G.↗
NASA NTRS2006

Tuning of MEMS Gyroscope using Evolutionary Algorithm and "Switched Drive-Angle" Method

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. We present the results of an experiment to determine the speed and efficiency of an evolutionary algorithm applied to electrostatic tuning of MEMS micro gyros. The MEMS gyro used in this experiment is a pyrex post resonator gyro (PRG) in a closed-loop control system. A measure of the quality of tuning is given by the difference in resonant frequencies, or frequency split, for the two orthogonal rocking axes. The current implementation of the closed-loop platform is able to measure and attain a relative stability in the sub-millihertz range, leading to a reduction of the frequency split to less than 100 mHz.

Micro-Electro-Mechanical Systems (MEMS)↗
NASA NTRS2018

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗
NASA NTRS2005

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.↗
NASA NTRS2006

An Interleaver Implementation for the Serially Concatenated Pulse-Position Modulation Decoder

We describe novel interleaver and deinterleaver architectures that support bandwidth efficient memory access for decoders of turbo-like codes that are used in conjunction with high order modulations. The presentation focuses on a decoder for serially concatenated pulse-position modulation (SCPPM), which is a forward-error-correction code designed by NASA to support laser communications from Mars at more than 50 megabits-per-second (Mbps). For 64-ary PPM, the new architectures effectively triple the fan-in of the interleaver and fan-out of the deinterleaver, enabling parallelization that doubles the overall throughput. The techniques described here can be readily modified for other PPM orders.

turbo decoding↗
NASA NTRS2017

Non-Maximally Decimated Filter Banks Enable Adaptive Frequency Hopping for Unmanned Aircraft Vehicles

In the last few years, radio technologies for unmanned aircraft vehicle (UAV) have advanced very rapidly. The increasing need to fly unmanned aircraft systems (UAS) in the national airspace system (NAS) to perform missions of vital importance to national security, defense, and science has pushed ahead the design and implementation of new radio platforms. However, a lot still has to be done to improve those radios in terms of performance and capabilities. In addition, an important aspect to account for is hardware cost and the feasibility to implement these radios using commercial off-the-shelf (COTS) components. UAV radios come with numerous technical challenges and their development involves contributions at different levels of the design. Cognitive algorithms need to be developed in order to perform agile communications using appropriate frequency allocation while maintaining safe and efficient operations in the NAS and, digital reconfigurable architectures have to be designed in order to ensure a prompt response to environmental changes. Command and control (C2) communications have to be preserved during "standard" operations while crew operations have to be minimized. It is clear that UAV radios have to be software-defined systems, where size, weight and power consumption (SWaP) are critical parameters. This paper provides preliminary results of the efforts performed to design a fully digital radio architecture as part of a NASA Phase I STTR. In this paper, we will explain the basic idea and technical principles behind our dynamic/adaptive frequency hopping radio for UAVs. We will present our Simulink model of the dynamic FH radio transmitter design for UAV communications and show simulation results and FPGA system analysis.

UAV↗
NASA NTRS2013

FPGA-Based X-Ray Detection and Measurement for an X-Ray Polarimeter

This technology enables detection and measurement of x-rays in an x-ray polarimeter using a field-programmable gate array (FPGA). The technology was developed for the Gravitational and Extreme Magnetism Small Explorer (GEMS) mission. It performs precision energy and timing measurements, as well as rejection of non-x-ray events. It enables the GEMS polarimeter to detect precisely when an event has taken place so that additional measurements can be made. The technology also enables this function to be performed in an FPGA using limited resources so that mass and power can be minimized while reliability for a space application is maximized and precise real-time operation is achieved. This design requires a low-noise, charge-sensitive preamplifier; a highspeed analog to digital converter (ADC); and an x-ray detector with a cathode terminal. It functions by computing a sum of differences for time-samples whose difference exceeds a programmable threshold. A state machine advances through states as a programmable number of consecutive samples exceeds or fails to exceed this threshold. The pulse height is recorded as the accumulated sum. The track length is also measured based on the time from the start to the end of accumulation. For track lengths longer than a certain length, the algorithm estimates the barycenter of charge deposit by comparing the accumulator value at the midpoint to the final accumulator value. The design also employs a number of techniques for rejecting background events. This innovation enables the function to be performed in space where it can operate autonomously with a rapid response time. This implementation combines advantages of computing system-based approaches with those of pure analog approaches. The result is an implementation that is highly reliable, performs in real-time, rejects background events, and consumes minimal power.

Gregory, Kyle↗
NASA NTRS2006

Three-Function Logic Gate Controlled by Analog Voltage

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Zebulum, Ricardo↗
NASA NTRS2010

Rapid Corner Detection Using FPGAs

In order to perform precision landings for space missions, a control system must be accurate to within ten meters. Feature detection applied against images taken during descent and correlated against the provided base image is computationally expensive and requires tens of seconds of processing time to do just one image while the goal is to process multiple images per second. To solve this problem, this algorithm takes that processing load from the central processing unit (CPU) and gives it to a reconfigurable field programmable gate array (FPGA), which is able to compute data in parallel at very high clock speeds. The workload of the processor then becomes simpler; to read an image from a camera, it is transferred into the FPGA, and the results are read back from the FPGA. The Harris Corner Detector uses the determinant and trace to find a corner score, with each step of the computation occurring on independent clock cycles. Essentially, the image is converted into an x and y derivative map. Once three lines of pixel information have been queued up, valid pixel derivatives are clocked into the product and averaging phase of the pipeline. Each x and y derivative is squared against itself, as well as the product of the ix and iy derivative, and each value is stored in a WxN size buffer, where W represents the size of the integration window and N is the width of the image. In this particular case, a window size of 5 was chosen, and the image is 640 480. Over a WxN size window, an equidistance Gaussian is applied (to bring out the stronger corners), and then each value in the entire window is summed and stored. The required components of the equation are in place, and it is just a matter of taking the determinant and trace. It should be noted that the trace is being weighted by a constant k, a value that is found empirically to be within 0.04 to 0.15 (and in this implementation is 0.05). The constant k determines the number of corners available to be compared against a threshold sigma to mark a valid corner. After a fixed delay from when the first pixel is clocked in (to fill the pipeline), a score is achieved after each successive clock. This score corresponds with an (x,y) location within the image. If the score is higher than the predetermined threshold sigma, then a flag is set high and the location is recorded.

Morfopoulos, Arin C.↗
NASA NTRS2011

Evaluation of Pulse Counting for the Mars Organic Mass Analyzer (MOMA) Ion Trap Detection Scheme

The Mars Organic Mass Analyzer is being developed at Goddard Space Flight Center to identify organics and possible biological compounds on Mars. In the process of characterizing mass spectrometer size, weight, and power consumption, the use of pulse counting was considered for ion detection. Pulse counting has advantages over analog-mode amplification of the electron multiplier signal. Some advantages are reduced size of electronic components, low power consumption, ability to remotely characterize detector performance, and avoidance of analog circuit noise. The use of pulse counting as a detection method with ion trap instruments is relatively rare. However, with the recent development of high performance electrical components, this detection method is quite suitable and can demonstrate significant advantages over analog methods. Methods A prototype quadrupole ion trap mass spectrometer with an internal electron ionization source was used as a test setup to develop and evaluate the pulse-counting method. The anode signal from the electron multiplier was preamplified. The an1plified signal was fed into a fast comparator for pulse-level discrimination. The output of the comparator was fed directly into a Xilinx FPGA development board. Verilog HDL software was written to bin the counts at user-selectable intervals. This system was able to count pulses at rates in the GHz range. The stored ion count nun1ber per bin was transferred to custom ion trap control software. Pulse-counting mass spectra were compared with mass spectra obtained using the standard analog-mode ion detection. Prelin1inary Data Preliminary mass spectra have been obtained for both analog mode and pulse-counting mode under several sets of instrument operating conditions. Comparison of the spectra revealed better peak shapes for pulse-counting mode. Noise levels are as good as, or better than, analog-mode detection noise levels. To artificially force ion pile-up conditions, the ion trap was overfilled and ions were ejected at very high scan rates. Pile-up of ions was not significant for the ion trap under investigation even though the ions are ejected in so-called 'ion-micro packets'. It was found that pulse counting mode had higher dynamic range than analog mode, and that the first amplification stage in analog mode can distort mass peaks. The inherent speed of the pulse counting method also proved to be beneficial to ion trap operation and ion ejection characterization. Very high scan rates were possible with pulse counting since the digital circuitry response time is so much smaller than with the analog method. Careful investigation of the pulse-counting data also allowed observation of the applied resonant ejection frequency during mass analysis. Ejection of ion micro packets could be clearly observed in the binned data. A second oscillation frequency, much lower than the secular frequency, was also observed. Such an effect was earlier attributed to the oscillation of the total plasma cloud in the ion trap. While the components used to implement pulse counting are quite advanced, due to their prevalence in consumer electronics, the cost of this detection system is no more than that of an analog mode system. Total pulse-counting detection system electronics cost is under $250

Van Amerom, Friso H.↗
NASA NTRS2011

NASA Tech Briefs, January 2011

The topics include: 1) Distributed Aerodynamic Sensing and Processing Toolbox; 2) Collaborative Supervised Learning for Sensor Networks; 3) Hazard Detection Software for Lunar Landing; 4) Onboard Nonlinear Engine Sensor and Component Fault Diagnosis and Isolation Scheme; 5) Network-Capable Application Process and Wireless Intelligent Sensors for ISHM; 6) Interface Supports Multiple Broadcast Transceivers for Flight Applications; 7) FPGA Sequencer for Radar Altimeter Applications; 8) Miniature Sapphire Acoustic Resonator - MSAR; 9) Process-Hardened, Multi-Analyte Sensor for Characterizing Rocket Plume Constituents; 10) SAD5 Stereo Correlation Line-Striping in an FPGA; 11) Hybrid Composite Cryogenic Tank Structure; 12) Nanoscale Deformable Optics; 13) Reliability-Based Design Optimization of a Composite Airframe Component; 14) Zinc Oxide Nanowire Interphase for Enhanced Lightweight Polymer Fiber Composites; 15) Plasma Igniter for Reliable Ignition of Combustion in Rocket Engines; 16) Wire Test Grip Fixture; 17) A Sub-Hertz, Low-Frequency Vibration Isolation Platform; 18) Carbon Nanofibers Synthesized on Selective Substrates for Nonvolatile Memory and 3D Electronics; 19) Nanoparticle/Polymer Nanocomposite Bond Coat or Coating; 20) High-Resolution Wind Measurements for Offshore Wind Energy Development; 21) Spring Tire; 22) Marsviewer 2008; 23) Mission Services Evolution Center Message Bus; 24) Major Constituents Analysis for the Vehicle Cabin Atmosphere Monitor; 25) Astronaut Health Participant Summary Application; 26) Adaption of the AMDIS Method to Flight Status on the VCAM Instrument; 27) Natural Language Interface for Safety Certification of Safety-Critical Software; 28) Cryogenic Caging for Science Instrumentation; 29) Wide-Range Neutron Detector for Space Nuclear Applications; 30) In Situ Guided Wave Structural Health Monitoring System; 31) Multiplexed Energy Coupler for Rotating Equipment; 32) Attitude Estimation in Fractionated Spacecraft Cluster Systems; 33) Full Piezoelectric Multilayer-Stacked Hybrid Actuation/Transduction Systems; 34) Active Flow Effectors for Noise and Separation Control; 35) Method and System for Temporal Filtering in Video Compression Systems; 36) Apparatus for Measuring Total Emissivity of Small, Low-Emissivity Samples; 37) Multiple-Zone Diffractive Optic Element for Laser Ranging Applications; 38) Simplified Architecture for Precise Aiming of a Deep-Space Communication Laser Transceiver; 39) Two-Photon-Absorption Scheme for Optical Beam Tracking; 40) High-Sensitivity, Broad-Range Vacuum Gauge Using Nanotubes for Micromachined Cavities; 41) Wide-Field Optic for Autonomous Acquisition of Laser Link; 42) Extracting Zero-Gravity Surface Figure of a Mirror; 43) Modeling Electromagnetic Scattering From Complex Inhomogeneous Objects; 44) Visual Object Recognition and Tracking of Tools; 45) Method for Implementing Optical Phase Adjustment; 46) Visual SLAM Using Variance Grid Maps; 47) Rapid Calculation of Spacecraft Trajectories Using Efficient Taylor Series Integration; 48) Efficient Kriging Algorithms; 49) Predicting Spacecraft Trajectories by the WeavEncke Method; 50) An Augmentation of G-Guidance Algorithms; 51) Comparison of Aircraft Icing Growth Assessment Software; 52) Silicon-Germanium Voltage-Controlled Oscillator at 105 GHz; 53) Estimation of Coriolis Force and Torque Acting on Ares-1; 54) Null Lens Assembly for X-Ray Mirror Segments; and 55) High-Precision Pulse Generator.

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