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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Cell Libraries

A NASA contract led to the development of faster and more energy efficient semiconductor materials for digital integrated circuits. Gallium arsenide (GaAs) conducts electrons 4-6 times faster than silicon and uses less power at frequencies above 100-150 megahertz. However, the material is expensive, brittle, fragile and has lacked computer automated engineering tools to solve this problem. Systems & Processes Engineering Corporation (SPEC) developed a series of GaAs cell libraries for cell layout, design rule checking, logic synthesis, placement and routing, simulation and chip assembly. The system is marketed by Compare Design Automation.

Source record↗
NASA NTRS2004

Resolving the Issues with Flywheel Position Sensors

For the past few years, the Advanced Electrical Systems Branch here at NASA Glenn has been pursuing research in the area of flywheels. The purpose of these pursuits has been t o explore the potential for flywheels to replace current battery-powered systems in space. So far it has been learned that flywheels offer large momentum storage capacity, comparatively small volume, high durability, and near- complete discharge capabilities, all of which are advancements over the existing nickel hydrogen and nickel cadmium batteries. Another significant advantage of flywheels is the potential they offer for combining the function of attitude control with energy storage. During the summer of 2004, I worked with Dr. Barbara Kenny in the Advanced Electrical Systems Branch, supporting the work she is doing by analyzing and testing some new components for the new Generation-2 flywheel. To monitor the speed and angular position of the flywheel rotor, a once-around (OAR) signal along with a sensorless algorithm is used. The OAR signal is used for the magnetic bearings that keep the flywheel suspended for frictionless operation. The sensorless algorithm is used for the flywheel motor/generator control. The OAR is generated from position sensors that monitor a circular plate. The plate has a cut down the middle such that one half of the circle is on a slightly lower level than the other. Every half-turn, or 180, the sensors detect the "cut" on the plate, and trigger the OAR, telling the computer that the rotor has made half a revolution. This, however, doesn't provide needed detailed information about the angular position of the rotor, since it only provides a signal alert every half- revolution. This is enough information for the magnetic bearing control but is insufficient for the motor/generator control. A new resolver was designed such that it would give continuous angle information rather than the 180 degree information of the OAR. The new resolver has two separate observable pieces: a flat middle section to monitor vertical motion, and an angled section around the circumference, which, when observed from above, produces a sine-wave displacement through the entire 360" revolution. My first job when I arrived this summer was to calibrate the sensors that would be mounted on the inside of the flywheel casing to monitor the position (angular and vertical) of the shaft. After calibration, I used the sensors to evaluate voltage outputs created by position differences between two pairs of sensors on the angled portion of the resolver for eight different angular positions, moving the resolver vertically and laterally through its entire potential range of motion. The results of these tests will be used to determine the rotor angular (and axial) position from the sensor readings once the new flywheel unit is assembled. The sensorless algorighm mentioned above consists of two operations: the signal injection method and the back electro-motive force (EMF). The signal injection is meant to work at low speeds, while the back EMF algorithm is meant to work at higher speeds. Both work together to determine the correct estimate of rotor position and speed based on the measured motor/generator current. It was determined that we wanted to know exactly how accurate our estimation methods were, and so a resolver (a commercially available mechanical sensor mounted to the motor/generator shaft to measure rotor position and speed) and a "Resolver to Digital" (R2D) circuit board was purchased to make the comparison to the existing estimation. My work related to the R2D board has included the following: creating two connector cables (one to power the circuit and one to get readable output off the board), writing Simulink code to process the board's output, and building a dSpace panel to control and monitor the circuit. The next step in the process will be to perform tests to compare the estimated rotor position and speed from the sensorless algorithm to the actual rotor and speed from the resolver signal.

Fehrmann, Elizabeth A.↗
NASA NTRS2004

Digital design using selection operations

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Whitaker, Sterling R.↗
NASA NTRS1989

Method and apparatus for measuring frequency and phase difference

A system for deriving direct digital indications of frequency and phase difference between two incoming pulse trains adaptable for collision avoidance systems or the like. A pair of radar beams 152 and 152A are directed toward a target 153 and corresponding beams 154 and 154A returning therefrom are detected. A digital difference circuit 110 forms a pulse train 66 from the Doppler shift frequencies of each beam pair having a repetition rate functionally related to the difference in magnitude of the shift frequencies. Pulses from the pulse train are counted as a function of time. Visual indications thereof on display 144 are correlative to target position relative to beams 152 and 152A.

Kobayashi, Herbert S.↗
NASA NTRS2009

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Buchner, S.↗
NASA NTRS2009

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗
NASA NTRS2003

Compact Interconnection Networks Based on Quantum Dots

Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary-signal wires described in the cited prior article. One of these advances would be the development of QCA-based wires capable of bidirectional transmission of signals. The other advance would be the development of QCA circuits capable of high-impedance state outputs. The high-impedance states would be utilized along with the 0- and 1-state outputs of QCA.

Fijany, Amir↗
NASA NTRS2015

Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications

A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.

Adell, Philippe C.↗
NASA NTRS1980

Biased-receiver digital interface

Coupling circuits converts TTL signals to higher voltage, higher current logic with good noise rejection. Depending on selected components, circuit may also be adapted to low-power applications.

Fitzgerald, F. C.↗
NASA NTRS1980

Independent synchronizer for digital decoders

Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.

Stiffler, J. J.↗
NASA NTRS2013

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Adell, Philippe↗
NASA NTRS2013

Single-event transient testing of low dropout PNP series linear voltage regulators

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Allen, Gregory↗
NASA NTRS2010

N channel JFET based digital logic gate structure

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Krasowski, Michael J.↗
NASA NTRS1968

Input gate circuit converted for use as linear amplifier

Commercially available integrated circuit that is marketed as a digital computer input gate circuit was converted to a linear amplifier in a microphone circuit that has high input impedance, low output impedance, low cost, and is small enough to fit on a standard printed circuit card.

Harper, T. P.↗
NASA NTRS1979

Digital correlator with fewer IC's

Digital correlator requires only few integrated circuits to determine synchronization of two 24-bit digital words. Circuit is easily reduced or expanded to accommodate shorter or longer words and can be utilized in industrial and commercial data processing and telecommunications.

Apple, G. G.↗