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At least 235 records · Page 13

Architectures and random properties of symplectic quantum circuits

Parametrized and random unitary (or orthogonal) n-qubit circuits play a central role in quantum information. As such, one could naturally assume that circuits implementing symplectic transformations would attract similar attention. However, this is not the case, as $\mathbb{SP}(d/2)$—the group of d × d unitary symplectic matrices—has thus far been overlooked. In this work, we aim at starting to fill this gap. We begin by presenting a universal set of generators $\mathcal{G}$ for the symplectic algebra $\mathfrak{sp}(d/2)$, consisting of one- and two-qubit Pauli operators acting on neighboring sites in a one-dimensional lattice. Here, we uncover two critical differences between such set, and equivalent ones for unitary and orthogonal circuits. Namely, we find that the operators in $\mathcal{G}$ cannot generate arbitrary local symplectic unitaries and that they are not translationally invariant. We then review the Schur–Weyl duality between the symplectic group and the Brauer algebra, and use tools from Weingarten calculus to prove that Pauli measurements at the output of Haar random symplectic circuits can converge to Gaussian processes. As a by-product, such analysis provides us with concentration bounds for Pauli measurements in circuits that form t-designs over $\mathbb{SP}(d/2)$. To finish, we present tensor-network tools to analyze shallow random symplectic circuits, and we use these to numerically show that computational-basis measurements anti-concentrate at logarithmic depth.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

VLSI Reed-Solomon Encoder With Interleaver

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek↗

Synthesis of single-qutrit circuits from Clifford+𝑅 gates

Here, we present two deterministic compilation algorithms for single-qutrit unitaries with O ( log 1 / ɛ ) gate depth. Each algorithm selects a nearby approximation to the target unitary and then exactly synthesizes the approximation over the Clifford + R basis. The first algorithm exhaustively searches over the group; while the second algorithm searches only for Householder reflections. The exhaustive search algorithm yields an average R count of 2.193 ( 11 ) + 8.621 ( 7 ) log 10 ( 1 / ɛ ) , albeit with a time complexity of O ( ɛ − 4.4 ) . The Householder search algorithm results in a larger average R count of 3.20 ( 13 ) + 10.77 ( 3 ) log 10 ( 1 / ɛ ) at a reduced time complexity of O ( ɛ − 0.42 ) , greatly extending the reach in ɛ . These costs correspond asymptotically to 35% and 69% more non-Clifford gates compared with synthesizing the same unitary with two qubits. Such initial results are encouraging for using the R gate as the nontransversal gate for qutrit-based computation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Scaling quantum approximate optimization on near-term hardware

The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.

97 MATHEMATICS AND COMPUTING↗

Nondestructive determination of the depth of planar p-n junctions by scanning electron microscopy

A method was developed for measuring nondestructively the depth of planar p-n junctions in simple devices as well as in integrated-circuit structures with the electron-beam induced current (EBIC) by scanning parallel to the junction in a scanning electron microscope (SEM). The results were found to be in good agreement with those obtained by the commonly used destructive method of lapping at an angle to the junction and staining to reveal the junction.

Chi, J.-Y.↗

High Temperature Superconductor/Semiconductor Hybrid Microwave Devices and Circuits

Contents include following: film deposition technique; laser ablation; magnetron sputtering; sequential evaporation; microwave substrates; film characterization at microwave frequencies; complex conductivity; magnetic penetration depth; surface impedance; planar single-mode filters; small antennas; antenna arrays phase noise; tunable oscillations; hybrid superconductor/semiconductor receiver front ends; and noise modeling.

Romanofsky, Robert R.↗

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗

Quasi-In-Situ Analysis of Electrode Top Atomic Layers via High-Sensitivity Low-Energy Ion Scattering and Potential-Controlled Sample Transfer

Electrocatalytic reactions involve interfacial interactions between the surfaces of electrodes and reactive species at an electrolyte interface. There are presently no universal or unambiguous methods to directly assay the active top atomic layer composition that influences the reactivity of these electrodes under relevant operating conditions. Low-energy ion scattering (LEIS) spectroscopy is a surface characterization technique that yields compositional analysis of the outermost atomic layer of a material, but it must be performed in ultrahigh vacuum (UHV). Application of LEIS measurements to electrochemical materials that are removed from ambient liquid-phase environments thus leaves an open question as to whether the surface that is transferred to UHV is truly the surface that manifested during the electrochemical reaction. Toward the goal of preserving the active surface state, we developed a sample transfer workflow for LEIS enabling air-free removal and drying of an electrode from an electrochemical cell while maintaining control of the potential using an auxiliary electrode. The potential-controlled emersion method was demonstrated to give distinct potential-dependent surface compositions for a Cu−Pd alloy relative to removal after uncontrolled return to open-circuit potential. A Cu-enriched surface was found at anodic potential and a Pd-enriched surface at cathodic potential, suggesting that the approach can be used to retain representative atomic configurations during transfer. Since adsorbates will often persist from the reaction environment, conventional sample pretreatment methods for removal, including atomic O and atomic H exposure, were also contrasted. Both methods were found to differ with results from incidental low-dose depth profiling by the LEIS primary ion source, which removes adventitious species and surface atoms during the course of repeated measurements. These depth profiles were found to be sensitive to sample history and thus qualitatively informative, despite the possible changes induced by ion damage. The results exhibit (i) the need for complete control over the polarization state of the sample at all times (no excursions to open circuit during transfer) and (ii) the utility of low-dose depth profiling to capture changes in the near-surface composition.

Alloys↗

Pitting Propagation Behavior on Low Alloy AISI 4130 (UNS G41300) Steel Exposed to Various Alkali and Alkaline Earth Metal Chlorides

Pit propagation studies were conducted to elucidate whether alkali and alkali earth metal cations such as Na+ and Rb+ present in the form of metal chloride salts such as RbCl affect pitting behavior in distinctly different manner than NaCl. Pit propagation studies were conducted on a low alloy steel using one-dimensional (1-D) pit method over pit depths from 300-1000 µm. LSV and EIS of planar electrodes of 4130 in a range of Cl- solutions were conducted and revealed no detected differences in impedance, open circuit, corrosion potential (Ecorr), passive current density (ipass), and pitting potential (Epit) as a function of salt type. In the case of one-dimensional pits during fast downward scan rates, the saturation potential (Esat) varied as a function of cation identity when pit depths were shallow. Mass transported limited current density also differed with cations in shallow pits when various alkali metal and alkaline metal cations were present. The limiting current density was increased for RbCl relative to NaCl The pit surface potential (Esurf) of activated pit surfaces reached Ecorr prior to establishing a condition where the pit electrolyte surface concentration (Csurf) was less than the critical concentration for active acidified pitting (i.e. Csurf<Ccrit) in this marginally passivating steel. For various Esurf and pit current density (ipit) combinations at constant Csurf where Ccrit< Csurf < Csat, E-log(i) plots were constructed using the method of Tianshu to create IR ohmic voltage corrected Tafel plots for various fixed pit solution concentrations. Under these conditions, the influence of cation identity on charge transfer controlled kinetics indicated slight differences in Tafel behavior where RbCl was slightly more aggressive than NaCl for low alloy steel oxidation. Differences in metal cation identity exert no effect on passive or breakdown on planar electrodes and only effect pit propagation stage in shallow pits.

Demarest, Chalres↗

Thermal stress cycling of GaAs solar cells

A thermal cycling experiment was performed on GaAs solar cells to establish the electrical and structural integrity of these cells under the temperature conditions of a simulated low-Earth orbit of 3-year duration. Thirty single junction GaAs cells were obtained and tests were performed to establish the beginning-of-life characteristics of these cells. The tests consisted of cell I-V power output curves, from which were obtained short-circuit current, open circuit voltage, fill factor, and cell efficiency, and optical micrographs, spectral response, and ion microprobe mass analysis (IMMA) depth profiles on both the front surfaces and the front metallic contacts of the cells. Following 5,000 thermal cycles, the performance of the cells was reexamined in addition to any factors which might contribute to performance degradation. It is established that, after 5,000 thermal cycles, the cells retain their power output with no loss of structural integrity or change in physical appearance.

Janousek, B. K.↗

Unlocking the Electrochemical–Mechanical Coupling Behaviors of Dendrite Growth and Crack Propagation in All-Solid-State Batteries

Dendrite growth and crack propagation are two major hurdles on the road towards the large-scale commercialization of lithium metal all-solid-state batteries (ASSBs). Due to the high multiphysics coupled nature of the underlying dendrite growth mechanism, understanding it has been difficult. Herein, for the first time, an electrochemical-mechanical model is established that directly couples dendrite growth and crack propagation from a physics-based perspective at the cell level. Results reveal that overpotential-driven stress propels a crack to penetrate through the solid electrolyte, creating vacancies for dendrite growth, leading to the short circuit of the battery. Thus, high lithiation/charging rate and low conductivity of electrolytes can accelerate the electrochemical failure of the battery. It is further discovered that Young's modulus E LLZO of the electrolyte has competing contributions to the fracture and dendrite growth; specifically, when E LLZO = 40-100 GPa, the short circuit is triggered early. A larger toughness value hinders the crack propagation and mitigates the Li dendrite growth. The developed multiphysics model provides an in-depth understanding of the coupling of crack propagation and dendrite growth within ASSBs and an insightful mechanistic design guidance map for robust and safe ASSB cells.

25 ENERGY STORAGE↗

Current status of silicon solar cell technology

Recent advances in solar cell technology have led to the development of laboratory cells with efficiencies above 15% and production cells with efficiencies in the area of 13%. The increased output is largely the result of increases in the short-circuit current. The most significant gain in the amount of light entering the cell has been obtained through surface texturing by chemical etching techniques. Sheet resistances resulting from phosphorus diffusion in the 800 C temperature range yield junction depths on the order of 0.1 micrometer, leading to significant increases in the blue region of the cell spectral response. The inclusion of a back surface field in 10 ohm-cm cells has produced an increase in open-circuit voltage of about 50 mV and an increase in the minority carrier lifetime. It appears that a low emitter efficiency of the diffused region is the cause of poor voltages. Future research will be primarily directed toward correcting this deficiency and toward the development of low cost production methods.

Brandhorst, H. W., Jr.↗

Recent Advancements in Reconfigurable mmWave Devices Based on Phase-Change and Metal Insulator Transition Materials

Chalcogenide Phase Change Materials (PCM) and metal insulator transition (MIT) materials are a group of materials that are capable of switching between low resistance and high resistance states. These emerging materials have been widely used in optical storage media and memory devices. Over the past recent years, there have been interests in exploiting the PCM and MIT materials, especially germanium antimony telluride (GST) alloys and vanadium dioxide (VO 2 ), for radio frequency (RF) applications. The PCM and MIT-based RF devices are expected to bridge the gap between semiconductor switches and microelectromechanical system (MEMS) switches as they combine the low insertion loss performance of MEMS technology and the small size and reliability performance of semiconductor technology. This article presents an overview of the PCM and MIT materials for RF circuits and discusses the recent advancements in reconfigurable millimeter-wave (mmWave) devices based on PCM and MIT materials in depth.

36 MATERIALS SCIENCE↗

Electron spectroscopy analysis

The Surface Science Laboratories at the University of Alabama in Huntsville (UAH) are equipped with x-ray photoelectron spectroscopy (XPS or ESCA) and Auger electron spectroscopy (AES) facilities. These techniques provide information from the uppermost atomic layers of a sample, and are thus truly surface sensitive. XPS provides both elemental and chemical state information without restriction on the type of material that can be analyzed. The sample is placed into an ultra high vacuum (UHV) chamber and irradiated with x-rays which cause the ejection of photoelectrons from the sample surface. Since x-rays do not normally cause charging problems or beam damage, XPS is applicable to a wide range of samples including metals, polymers, catalysts, and fibers. AES uses a beam of high energy electrons as a surface probe. Following electronic rearrangements within excited atoms by this probe, Auger electrons characteristic of each element present are emitted from the sample. The main advantage of electron induced AES is that the electron beam can be focused down to a small diameter and localized analysis can be carried out. On the rastering of this beam synchronously with a video display using established scanning electron microscopy techniques, physical images and chemical distribution maps of the surface can be produced. Thus very small features, such as electronic circuit elements or corrosion pits in metals, can be investigated. Facilities are available on both XPS and AES instruments for depth-profiling of materials, using a beam of argon ions to sputter away consecutive layers of material to reveal sub-surface (and even semi-bulk) analyses.

Gregory, John C.↗

The potential of np GaAs solar cells for high efficiency concentrator applications

This communication considers the design of the front grid contact of np GaAs solar cells for high efficiency concentrator applications. This design involves shadowing, contact resistance, and active layer sheet resistance losses, and at high concentrations, the power loss due to voltage drop on the resistance of the grid fingers should be considered. Analysis of the performance can be calculated as a function of junction depth and surface recombination velocity. The junction depth can be optimized by considering its effect on the collection efficiency of the dark current-voltage characteristics or the open circuit voltage, and on the series resistance loss or the fill factor for material parameters. The choice of the material parameters, calculation of the short circuit current, the selection of the n layer thickness, and the cell maximum power and efficiency are discussed. It is concluded that optimized multi-grid structures should allow the use of 10 by 10 sq cm cells with good efficiencies at high concentration ratios, and efficiencies of 22 to 25% should be obtainable from large area cells at concentrations of 40 AM1.

Flat, A.↗

Formation of a pn junction on an anisotropically etched GaAs surface using metalorganic chemical vapor deposition

A continuous p-type GaAs epilayer has been deposited on an n-type sawtooth GaAs surface using MOCVD. A wet chemical etching process was used to expose the intersecting (111)Ga and (-1 -1 1)Ga planes with 6-micron periodicity. Charge-collection microscopy was used to verify the presence of the pn junction thus formed and to measure its depth. The ultimate goal of this work is to fabricate a V-groove GaAs cell with improved absorptivity, high short-circuit current, and tolerance to particle radiation.

Leon, R. P.↗

Dual-unitary shadow tomography

We introduce a classical shadow tomography scheme based on dual-unitary brick-wall circuits termed "dual-unitary shadow tomography" (DUST). For this we study operator spreading and Pauli weight dynamics in one-dimensional qubit systems, evolved by random two-local dual-unitary gates arranged in a brick-wall structure, ending with a final measurement layer. We do this by deriving general constraints on the Pauli weight transfer matrix and specializing to the case of dual-unitarity. We first show that dual-unitaries must have a minimal amount of entropy production. Remarkably, we find that operator spreading in these circuits have a rich structure resembling that of relativistic quantum field theories, with massless chiral excitations that can decay or fuse into each other, which we call left- or right-movers. We develop a mean-field description of the Pauli weight in terms of $\rho(x,t)$, which represents the probability of having nontrivial support at site $x$ and depth $t$ starting from a fixed weight distribution. We develop an equation of state for $\rho(x,t)$, and simulate it numerically using Monte Carlo simulations. Lastly, we demonstrate that the fast-thermalizing properties of dual-unitary circuits make them better at predicting large operators than shallow brick-wall Clifford circuits. Our results are robust to finite-size effects due to the chirality of dual-unitary brick-wall circuits.

97 MATHEMATICS AND COMPUTING↗

Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0

This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

Shalf, JohnM. [Lawrence Berkeley National Laborato↗