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At least 235 records · Page 13

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Focal Plane Assembly↗

Hybrid CMOS System-on-Chip / InP MMIC Systems for Deep-Space Planetary Exploration at mm-Wave and THz

This paper discusses the applicability of hybrid CMOS/InP-MMIC mm-Wave systems to remote sensing instrumentation for space exploration in Earth and Planetary science. We review the need for lower power and lighter weight instruments to accommodate the limited payload resources of exploration spacecraft, and then demonstrate how hybrid systems can address these challenges. An example hybrid CMOS-InP radiometer operating at 100 GHz is discoursed in detail including circuit & system design, interfacing and packaging techniques. Measurements are presented showing that the hybrid approach does not compromise instrument sensitivity.

Tang, Adrian↗

CMOS Charged Particle Spectrometers

Integrated circuits manufactured in CMOS technology, have been developed as diffusion-based charged particle spectrometers for space applications. A four-chip spectrometer designed to count protons and heavier ions was flown on the Clementine spacecraft, and the spectrometer proton response is compared to GOES-6 proton data for the 21 Feb. 1994 solar proton event.

charged↗

Interim test status report for NEPP scaled CMOS

This document serves as the fiscal year end report for the NEPP scaled complementary metal-oxide semiconductor (CMOS) task. Much of the effort this year focused on development of test capability and initial collection of data on SDRAM devices. Since the system has only just begun (in the last four weeks) to gather data, this report focuses on the test system and preliminary results.

Guertin, Steven M.↗

Modeling the effects of hydrogen and dose rate sensitivity in CMOS and bipolar technologies

Low dose rate (LDR) and high dose rate (HDR) experiments on field-oxide-field-effect-transistors (FOXFETs) and gated lateral pnp (GLPNP) bipolar transistors indicate that there is a dose rate enhancement factor (EF) associated with radiation-induced degradation. This EF is also affect by the presence of hydrogen in the oxide. In this work, we developed a one dimensional (1-D) numerical calculations code to investigate the key mechanisms that describe the dose rate sensitivity and the effect of hydrogen on dose rate effects. We used a finite-difference methodology for the numerical calculations that allow for computing solutions for the densities of the mobile species as well as for the electrostatic potential at nodes contained within a mesh superimposed on the solution domain. Results from calculations of damage EF indicate that oxide thickness, distribution of hole traps and hole capture cross-section affect dose rate sensitivity. In addition, calculations show that molecular hydrogen cracking at positively charged defects may be a key reaction relating hydrogen and dose rate response. Comparison to experimental data on bipolar and CMOS devices results in good agreement with the dose rate calculations of interface trap buildup

Barnaby, Hugh↗

A 294 GHz 0.47m W Caterpillar amplifier based transmitter in 65 nm CMOS for THz data-links

A fully integrated CMOS THz transmitter for short range data-links is presented which provides 0.47 mW of output power to 294 GHz. The output frequency is derived from a 147 GHz on-chip LO and fully differential caterpillar power amplifier combined with a transformer coupled frequency doubler. The transmitter is integrated with an on-chip dipole antenna for use in THz communication systems and consumes a total of 258 mW.

Chang, Mau-Chung Frank↗

A Sub-THz CMOS Molecular Clock with 20 ppt Stability at 10,000 s Based on A Dual-Loop Spectroscopic Detection and Digital Frequency Error Integration

This paper presents a dual-loop chip-scale molecular clock (CSMC), which enhances the Allan Deviation performance by combining high signal-to-noise ratio of using fundamental mode and long-term stability of using higher order modes in derivative molecular absorption spectroscopy. In addition, digital frequency-error integration is adopted in the frequency-locked loop to provide an infinite open-loop DC gain, which fully suppresses any frequency drift caused by the temperature-sensitive crystal oscillator. This new generation CSMC is implemented in 65-nm CMOS, and achieves 20 ppt (part-per-trillion) Allan Deviation at 10,000 s averaging time with 71-mW power consumption.

Han, Ruonan↗

CACTUS: A depleted monolithic active timing sensor using a CMOS radiation hard technology

The planned luminosity increase at the Large Hadron Collider in the coming years has triggered interest in the use of the particles' time of arrival as additional information in specialized detectors to mitigate the impact of pile-up. The required time resolution is of the order of tens of picoseconds, with a spatial granularity of the order of 1 mm. A time measurement at this precision level will also be of interest beyond the LHC and beyond high energy particle physics. We present in this paper the first developments towards a radiation hard Depleted Monolithic Active Pixel Sensor (DMAPS), with high-resolution time measurement capability. The technology chosen is a standard high voltage CMOS process, in conjunction with a high resistivity detector material, which has already proven to efficiently detect particles in tracking applications after several hundred of Mrad of irradiation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process

This paper presents a low jitter dual-path chargepump phase locked loop (PLL) synthesizer in a CMOS 65-nm process for quantum readout applications. The PLL incorporates a programmable dual chargepump and a loop filter with both proportional and integral paths that can be driven independently providing flexible control of the loop bandwidth to achieve low jitter performance. The design is implemented at 300 K and critical blocks like voltage-controlled oscillator (VCO) and chargepump (CP) are analyzed at 77 K based on the characterized results. The LC-VCO is realized with the class-C NMOS only architecture with 5-bit coarse control and quadrature signals are generated with poly phase filter. The VCO is designed with the tuning range of 1 GHz around the center frequency of 6 GHz with Phase Noise of -123 dBc/Hz and -132 dBc/Hz at 1MHz offset at 300 K and 77 K temperature. The simulated PLL rms jitter is 125 fs at 6 GHz with a power consumption of 8 mW at the 1.2 V power supply.

47 OTHER INSTRUMENTATION↗

Topmetal CMOS direct charge sensing plane for neutrinoless double-beta decay search in high-pressure gaseous TPC

We propose a novel charge sensing concept for high-pressure Time Projection Chamber (TPC) to search for Neutrinoless Double-Beta Decay (NLDBD) with ton-scale isotope mass and beyond. A meter-sized plane, tiled with an array of CMOS integrated sensors called Topmetal that directly collect charge without gas avalanche gain, is to be deployed into a high-pressure gaseous TPC with working gases containing suitable NLDBD candidate isotopes such as Xe-136 and Se-82. The Topmetal sensor has an electronic noise <30 e- per pixel, which allows the detector to reach <1% FWHM energy resolution at the NLDBD Q-value for both Xe-136 and 82SeF6 gases by measuring ionization charges alone. The elimination of charge avalanche gain allows the direct sensing of slow-drifting ions, which enables the use of highly electronegative gas SeF6 in which free electrons do not exist. It supports the swapping of working gases without hardware modification, which is a unique way to validate signals against radioactive backgrounds. Since the sensor manufacturing and plane assembling could leverage unaltered industrial mass-production processes, stability, uniformity, scalability, and cost-effectiveness that are required for ton-scale experiments could all be reached. The strengths of TPC such as 3D ionization tracking and decay daughter tagging are retained. This development could lead to a competitive NLDBD experiment at and above ton-scale. The conceptual considerations, simulations, and initial prototyping are discussed.

Mei, Yuan↗

Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Hybrid MEMS-CMOS ion traps for NISQ computing

Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. Finally, we also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures

Allan deviation provides a means to characterize the time-dependence of noise in oscillators and potentially identify the source characteristics. Measurements on a 130 nm, 7-stage ring oscillator show that the Allan deviation declines from 300 K to 150 K as expected, but surprisingly increases from 150 K to 11 K. At low temperatures, the measured Allan deviation can be well fit using a few random telegraph noise (RTN) sources over the range of a few kilohertz to a few gigahertz. Further, the RTN characteristics evolve to reveal an enhanced role in low-frequency noise at lower temperatures.

47 OTHER INSTRUMENTATION↗