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At least 217 records · Page 12

Low cost silicon solar array project silicon materials task

A program was established to develop a high temperature silicon production process using existing electric arc heater technology. Silicon tetrachloride and a reductant will be injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction is expected to occur and proceed essentially to completion, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection of the molten silicon will be developed using standard engineering approaches, and the salt vapor will later be electrolytically separated into its elemental constituents for recycle. Preliminary technical evaluations and economic projections indicate not only that this process appears to be feasible, but that it also has the advantages of rapid, high capacity production of good quality molten silicon at a nominal cost.

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Quality control during IC processing

Manual gives detailed test procedures for controlling silicon-wafer processing in manufacture of integrated circuits. Included among 43 test procedures are: ionic, bacterial, and solids contamination of high-purity water needed for wafer processing; crystallographic reflection, purity, and orientation; substrate dimensions and finish; thickness of deposited epitaxial films; oxide quality; photoresist characteristics; pinholes in insulating layers; metallized adhesion; and quality of ohmic contact.

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Process Research on Polycrystalline Silicon Material (PROPSM)

Results of hydrogen-passivated polycrystalline silicon solar cells are summarized. Very small grain or short minority-carrier diffusion length silicon was used. Hydrogenated solar cells fabricated from this material appear to have effective minority-carrier diffusion lengths that are still not very long, as shown by the open-circuit voltages of passivated cells that are still significantly less than those of single-crystal solar cells. The short-circuit current of solar cells fabricated from large-grain cast polycrystalline silicon is nearly equivalent to that of single-crystal cells, which indicates long bulk minority-carrier diffusion length. However, the open-circuit voltage, which is sensitive to grain boundary recombination, is sometimes 20 to 40 mV less. The goal was to minimize variations in open-circuit voltage and fill-factor caused by defects by passivating these defects using a hydrogenation process. Treatments with molecular hydrogen showed no effect on large-grain cast polycrystaline silicon solar cells.

Culik, J. S.↗

Technoeconomic Analysis of High-Value, Crystalline Silicon Photovoltaic Module Recycling Processes

Recycling is an important circular economy strategy, and for photovoltaics (PV), the one that has received the greatest research attention. Recycling of PV modules is required in Europe; everywhere else it competes in the market of end-of-life options, where cost is a primary decision factor. The vast majority of PV modules sold globally are crystalline-silicon (c-Si); most of the rest of the market are cadmium telluride thin film modules whose primary manufacturer runs its own commercial-scale recycling program. While many different c-Si recycling approaches and technologies have been proposed, they generally lack accompanying cost estimates or enough process information to model costs. Herein we develop detailed estimates of seven categories of capital and operating costs along with estimates of revenue from recovered materials for each step in two proposed recycling processes for c-Si PV modules. Using these results, we develop a hypothetical third recycling process merging process steps from the original two, estimate surcharges required to achieve minimum sustainable prices for each recycling process, as well as consider how economies of scale could reduce costs. Increasing the purity of and identifying higher-value markets for recovered materials are approaches to reducing costs and increasing recycling rates in voluntary markets.

crystalline silicon↗

Effects of processing and dopant on radiation damage removal in silicon solar cells

Gallium and boron doped silicon solar cells, processed by ion implantation followed by either laser or furnace anneal were irradiated by 1 MeV electrons and their postirradiation recovery by thermal annealing was determined. During the postirradiation anneal, gallium doped cells prepared by both processes recovered more rapidly and exhibited none of the severe reverse annealing observed for similarly processed 2 ohm-cm boron doped cells. Ion implanted furnace annealed 0.1 ohm-cm boron doped cells exhibited the lowest post-irradiation annealing temperatures after irradiation. The drastically lowered recovery temperature is attributed to the reduced oxygen and carbon content of the 0.1 ohm-cm cells. Analysis based on defect properties and annealing kinetics indicates that further reduction in annealing temperature is attainable with further reduction in the silicon's carbon and/or divacancy content after irradiation.

Weinberg, I.↗

Effects of processing and dopant on radiation damage removal in silicon solar cells

Gallium and boron doped silicon solar cells, processed by ion-implantation followed by either laser or furnace anneal were irradiated by 1 MeV electrons and their post-irradiation recovery by thermal annealing determined. During the post-irradiation anneal, gallium-doped cells prepared by both processes recovered more rapidly and exhibited none of the severe reverse annealing observed for similarly processed 2 ohm-cm boron doped cells. Ion-implanted furnace annealed 0.1 ohm-cm boron doped cells exhibited the lowest post-irradiation annealing temperatures (200 C) after irradiation to 5 x 10 to the 13th e(-)/sq cm. The drastically lowered recovery temperature is attributed to the reduced oxygen and carbon content of the 0.1 ohm-cm cells. Analysis based on defect properties and annealing kinetics indicates that further reduction in annealing temperature should be attainable with further reduction in the silicon's carbon and/or divacancy content after irradiation.

Weinberg, I.↗

Process Research On Polycrystalline Silicon Material (PROPSM)

The performance-limiting mechanisms in large-grain (greater than 1 to 2 mm in diameter) polycrystalline silicon solar cells were investigated by fabricating a matrix of 4 sq cm solar cells of various thickness from 10 cm x 10 cm polycrystalline silicon wafers of several bulk resistivities. Analysis of the illuminated I-V characteristics of these cells suggests that bulk recombination is the dominant factor limiting the short-circuit current. The average open-circuit voltage of the polycrystalline solar cells is 30 to 70 mV lower than that of co-processed single-crystal cells; the fill-factor is comparable. Both open-circuit voltage and fill-factor of the polycrystalline cells have substantial scatter that is not related to either thickness or resistivity. This implies that these characteristics are sensitive to an additional mechanism that is probably spatial in nature. A damage-gettering heat-treatment improved the minority-carrier diffusion length in low lifetime polycrystalline silicon, however, extended high temperature heat-treatment degraded the lifetime.

Culik, J. S.↗

Process research on non-CZ silicon material

High risk, high payoff research areas associated with he process for producing photovoltaic modules using non-CZ sheet material are investigated. All investigations are being performed using dendritic web silicon, but all processes are directly applicable to other ribbon forms of sheet material. The technical feasibility of forming front and back junctions in non-CZ silicon using liquid dopant techniques was determined. Numerous commercially available liquid phosphorus and boron dopant solutions are investigated. Temperature-time profiles to achieve N(+) and P(+) sheet resistivities of 60 + or - 10 and 40 + or - s10 ohms per square centimeter respectively are established. A study of the optimal method of liquid dopant application is performed. The technical feasibility of forming a liquid applied diffusion mask to replace the more costly chemical vapor deposited SiO2 diffusion mask was also determined.

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Triangular cross-section beam splitters in silicon carbide for quantum information processing

Abstract Triangular cross-section color center photonics in silicon carbide is a leading candidate for scalable implementation of quantum hardware. Within this geometry, we model low-loss beam splitters for applications in key quantum optical operations such as entanglement and single-photon interferometry. We consider triangular cross-section single-mode waveguides for the design of a directional coupler. We optimize parameters for a 50:50 beam splitter. Finally, we test the experimental feasibility of the designs by fabricating triangular waveguides in an ion beam etching process and identify suitable designs for short-term implementation.

42 ENGINEERING↗

Development and evaluation of die materials for use in the growth of silicon ribbons by the inverted ribbon growth process, task 2, LSSA project

Silicon sessile drop experiments were performed on a variety of commercially available refractory carbides, nitrides, oxides, and borides to examine the potential of these materials for applications involving either direct contact with molten silicon or as substrates for CVD coatings in the fabrication of dies and crucibles for containing molten silicon. Simultaneous experiments were also conducted with CVD layers of SiC, Si3N4, and SiOxNy. Silicon nitride layers, deposited with NH3:SiH4 ratios ranging from 100:1 down to 5:1, were examined in sessile drop experiments to determine if the layers are degraded as a result of using lower reagent ratios. Preliminary experiments were undertaken on the stability of CVD Si3N4 near the melting point of silicon. Silicon ribbon segments were grown from vitreous carbon dies which had been coated with CVD Si3N4. Depending upon the purity of the die materials, ribbon resistivity values up to 40 Omega cm were obtained.

Duffy, M. T.↗

Process-induced defects in solar cell silicon

The microstructure of as-grown and processed, edge-defined film-fed grown, silicon ribbons was studied in order to identify the basic mechanisms responsible for the change of the as-grown defect structure during processing at elevated temperatures. The short heat treatment required to diffuse the p-n junction was sufficient to cause heterogeneous precipitation of impurity atoms, particularly transition metals. In addition, an elastic recovery of the ribbon occurred by dislocation glide, resulting in the formation of a polygonizationlike structure of subboundaries in the base. Mechanisms are suggested by which twin boundaries, acting as dislocation obstacles, can concentrate the relatively low average dislocation densities typical of edge-defined film-fed grown ribbons (10 to the 4th to 10 to the 8th/sq cm) to values which are sufficient to induce the formation of subgrainlike boundary structures.

Gleichmann, R.↗

Process development of beam-lead silicon-gate COS/MOS integrated circuits

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Baptiste, B.↗

Development of processing procedures for advanced silicon solar cells

Ten ohm-cm silicon solar cells, 0.2 mm thick, were produced with short circuit current efficiencies up to thirteen percent and using a combination of recent technical advances. The cells were fabricated in conventional and wraparound contact configurations. Improvement in cell collection efficiency from both the short and long wavelengths region of the solar spectrum was obtained by coupling a shallow junction and an optically transparent antireflection coating with back surface field technology. Both boron diffusion and aluminum alloying techniques were evaluated for forming back surface field cells. The latter method is less complicated and is compatible with wraparound cell processing.

Scott-Monck, J. A.↗

Gravitational effects of process-induced dislocations in silicon

Matters pertaining to semiconductor device fabrication were studied in terms of the influence of gravity on the production of dislocations in silicon wafers during thermal cycling in a controlled ambient where no impurities are present and oxidation is minimal. Both n-type and p-type silicon wafers having a diameter of 1.25 in to 1.5 in, with fixed orientation and resistivity values, were used. The surface dislocation densities were measured quantitatively by the Sirtl etch technique. The results show two significant features of the plastic flow phenomenon as it is related to gravitational stress: (1) the density of dislocations generated during a given thermal cycle is directly related to the duration of the cycle; and (2) the duration of the thermal cycle required to produce a given dislocation density is inversely related to the equilibrium temperature. Analysis of the results indicates that gravitational stress is instrumental in process-induced defect generation.

Porter, W. A.↗

Fine Collimator Grids Using Silicon Metering Structure

The project Fine Collimator Grids Using Silicon Metering Structure was managed by Dr. Carol Eberhard of the Electromagnetic Systems & Technology Department (Space & Technology Division) of TRW who also wrote this final report. The KOH chemical etching of the silicon wafers was primarily done by Dr. Simon Prussin of the Electrical Engineering Department of UCLA at the laboratory on campus. Moshe Sergant of the Superconductor Electronics Technology Department (Electronics Systems & Technology Division) of TRW and Dr. Prussin were instrumental in developing the low temperature silicon etching processes. Moshe Sergant and George G. Pinneo of the Microelectronics Production Department (Electronics Systems & Technology Division) of TRW were instrumental in developing the processes for filling the slots etched in the silicon wafers with metal-filled materials. Their work was carried out in the laboratories at the Space Park facility. Moshe Sergant is also responsible for the impressive array of Scanning Electron Microscope images with which the various processes were monitored. Many others also contributed their time and expertise to the project. I wish to thank them all.

Eberhard, Carol↗

Solution Processed Schottky Diodes Enabled by Silicon Carbide Nanowires for Harsh Environment Applications

Silicon carbide nanowires (SiC NWs) exhibit promising features to allow solution-processable electronics to be deployed in harsh environments. By utilizing a nanoscale form of SiC, we were able to disperse the material into liquid solvents, while maintaining the resilience of bulk SiC. Here, this letter reports the fabrication of SiC NW Schottky diodes. Each diode consisted of just one nanowire with an approximate diameter of 160 nm. In addition to analyzing the diode performance, the effects of elevated temperatures and proton irradiation on the current–voltage characteristics of SiC NW Schottky diodes were also examined. The device could maintain similar values for ideality factor, barrier height, and effective Richardson constant upon proton irradiation with a fluence of 10 16 ion/cm 2 at 873 K. As a result, these metrics have clearly demonstrated the high-temperature tolerance and irradiation resistance of SiC NWs, ultimately indicating that they may provide utility in allowing solution-processable electronics in harsh environments.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Investigation of single-event upset (SEU) in an advanced bipolar process

An extensive analytical and experimental study SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes.

Zoutendyk, John A.↗

Tribological properties of silicon carbide in metal removal process

This paper reviews material properties of adhesion, friction and wear of single-crystal silicon carbide in contact with metals and alloys involved in a metal removal process such as grinding. The tribological properties in the metal removal processes are divided into properties which remove metal by adhesion between sliding surfaces, and metal removal by silicon carbide sliding against a metal, indenting it, and plowing a series of grooves or furrows. The paper also deals with fracture and deformation characteristics of the silicon carbide surface; the adhesion, friction and metal transfer to silicon carbide is related to the relative chemical activity of the metals. Atomic size and content of alloying elements play a dominant role in controlling adhesion and friction properties of alloys. The friction and abrasive wear decrease as the shear strength of the bulk metal increases.

Miyoshi, K.↗