A Prony-based curve-fitting method for characterization of RF pulses from optoelectronic devices
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Many recipes for realizing topological superconductivity rely on broken time-reversal symmetry, which is often attained by applying a substantial external magnetic field. Alternatively, using magnetic materials can offer advantages through low-field operation and design flexibility on the nanoscale. Mechanisms for lifting spin degeneracy include exchange coupling, spin-dependent scattering, spin injection – all requiring direct contact between the bulk or induced superconductor and a magnetic material. Here, we implement locally broken time-reversal symmetry through dipolar coupling from nearby micromagnets to superconductor-semiconductor hybrid nanowire devices. Josephson supercurrent is hysteretic due to micromagnets switching. At or around zero external magnetic field, we observe an extended presence of Andreev bound states near zero voltage bias. We also show a zero-bias peak plateau of a non-quantized value. Our findings largely reproduce earlier results where similar effects were presented in the context of topological superconductivity in a homogeneous wire, and attributed to more exotic time-reversal breaking mechanisms [Nat. Phys. 17, 43 (2020)]. In contrast, our stray field profiles are not designed to create Majorana modes, and our data are compatible with a straightforward interpretation in terms of trivial states in quantum dots. At the same time, the use of micromagnets in hybrid superconductor-semiconductor devices shows promise for future experiments on topological superconductivity.
Abstract Monoclinic gallium oxide (β-Ga 2 O 3 ) is attracting intense focus as a material for power electronics, thanks to its ultra-wide bandgap (4.5–4.8 eV) and ability to be easily doped n -type. Because the holes self-trap, the band-edge luminescence is weak; hence, β-Ga 2 O 3 has not been regarded as a promising material for light emission. In this work, optical and structural imaging methods revealed the presence of localized surface defects that emit in the near-UV (3.27 eV, 380 nm) when excited by sub-bandgap light. The PL emission of these centers is extremely bright—50 times brighter than that of single-crystal ZnO, a direct-gap semiconductor that has been touted as an active material for UV devices.
In this work, all-back-contact thin film photovoltaic devices in lattice back contact (LBC) configuration are studied by device simulation to set the requirements for achieving efficiency > 20% with lateral contact spacing > 50 µm. The numerical device model is first validated against published data for an LBC perovskite device and extended to predict the performance of Cd(Se,Te)-based polycrystalline devices. Recent advances in the electronic properties of Cd(Se,Te) films have made high efficiency LBC devices feasible with industrially-scalable contact dimensions. Constraints on bulk, interface, and contact properties are quantified and discussed
Two types of cadmium selenide telluride (CdSeTe) photovoltaic devices have been exposed to high-energy (150–1500 keV) protons with fluences ranging from 1 × 10 11 to 9 × 10 13 cm −2 . Pre- and post-irradiation current density vs voltage characteristic data were collected and analyzed. Arsenic-doped CdSeTe devices retained 80% of the power conversion efficiency (PCE) relative to control devices after exposure to 10 12 cm −2 650 keV protons, while copper-doped CdSeTe devices retained about 95% of the control PCE under the same irradiation condition. Displacement damage dose analysis coupled with simulations for duration-dependent performance in a medium Earth orbit space mission revealed superior PCE remaining factors, indicating greater resilience to proton bombardment than state-of-the-art multijunction III-V based space photovoltaic technologies.
Ferroelectric materials have been widely researched for applications in memory and energy storage. Among these materials and benefiting from their excellent chemical compatibility with complementary metal–oxide–semiconductor (CMOS) devices, hafnia-based ferroelectric thin films hold great promise for highly scaled semiconductor memories, including nonvolatile ferroelectric capacitors and transistors. However, variation in the switched polarization of this material during field cycling and a limited understanding of the responsible mechanisms have impeded their implementation in technology. Here, we show that ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) capacitors that are nearly free of polarization “wake-up”─a gradual increase in switched polarization as a function of the number of switching cycles─can be achieved by introducing ultrathin HfO 2 buffer layers at the HZO/electrodes interface. High-resolution transmission electron microscopy (HRTEM) reveals crystallite sizes substantially greater than the film thickness for the buffer layer capacitors, indicating that the presence of the buffer layers influences the crystallization of the film (e.g., a lower ratio of nucleation rate to growth rate) during postdeposition annealing. This evidently promotes the formation of a polar orthorhombic (O) phase in the as-fabricated buffer layer samples. Synchrotron X-ray diffraction (XRD) reveals the conversion of the nonpolar tetragonal (T) phase to the polar orthorhombic (O) phase during electric field cycling in the control (no buffer) devices, consistent with the polarization wake-up observed for these capacitors. The extent of T–O transformation in the nonbuffer samples is directly dependent on the duration over which the field is applied. Here these results provide insight into the role of the HZO/electrodes interface in the performance of hafnia-based ferroelectrics and the mechanisms driving the polarization wake-up effect.
We present a unified thermionic emission (TE) and thermionic-field emission (TFE) model for the ideal reverse-bias leakage current in Schottky junctions. The unified TE–TFE analytical model advances upon previous analytical TFE models by Murphy–Good and Padovani–Stratton, which are the two most widely adopted models by the community, in two major aspects: (i) the applicability of the TFE expression therein is extended to near-zero surface electric fields by an error-function correction, allowing for the calculation of the total current by a nontrivial sum of TE (over-the-barrier current) and TFE (below-the-barrier current) contributions; therefore, an accurate description of the TE-to-TFE transition region is captured analytically for the first time; (ii) image-force lowering is considered with much-simpler correction terms. Comparisons with the reference numerical model show that the unified TE–TFE model has excellent accuracy, as well as a 10 000× reduction in computation time. The unified model is further tested against experimental data from Schottky barrier diodes based on Si, 4H-SiC, GaN, and β-Ga 2 O 3 , revealing accurate extractions of barrier heights and correct descriptions of the ideal reverse leakage characteristics. With the extended applicable range, improved accuracy, and computational efficiency, the unified TE–TFE model is highly valuable for the design and analysis of devices based on Schottky junctions, as well as for potential integration in technology computer-aided design (TCAD) tools.
A device employing the generation and enhancement of surface acoustic waves on a highly doped p-type III-V semiconductor substrate (e.g., GaAs, GaSb, InAs, or InGaAs). The device includes two SiO 2 /ZnO islands, each including a SiO 2 buffer layer deposited on the doped p-type III-V semiconductor substrate and a ZnO layer deposited on the SiO 2 buffer layer. An input interdigital transducers (IDT) and an output IDT are each patterned on one of the SiO 2 /ZnO islands. The IDTs generates surface acoustic waves along an exposed surface of the highly doped p-type III-V semiconductor substrate. The surface acoustic waves improve the photoelectric and photovoltaic properties of the device. The device is manufactured using a disclosed technique for propagating strong surface acoustic waves on weak piezoelectric materials. Also disclosed is a photodetector developed using that technique.
This contribution explores an alternate route to forming pinhole-based poly-Si/dielectric/c-Si passivating contacts. The method utilizes controlled dielectric breakdown or electroforming to produce nanoscale pinholes in a thick (non-tunnelling) dielectric which, when annealed, allows dopant atoms to pass from doped poly-Si through the pinholes and into the c-Si wafer, forming conductive pathways. We show that the pinholes lose passivation after electroforming but can be repassivated with a forming gas anneal. N-type contacts show contact resistivities of ~20 mOhm-cm2, but p-type contacts are ~100 mOhm-cm2. Devices show a distinct kink in the J-V curve indicative of a barrier to transport. The method can be expanded to optimized dielectric passivation stacks (not just thin, single layers) and can be formed in parallel over the faces of the wafer in selected areas (pinholes only under the grid lines).
Semiconductor quantum dot devices can be challenging to configure into a regime where they are suitable for qubit operation. This challenge arises from variations in gate control of quantum dot electron occupation and tunnel coupling between quantum dots on a single device or across several devices. Furthermore, a single control gate usually has capacitive coupling to multiple quantum dots and tunnel barriers between dots. If the device operator, be it human or machine, has quantitative knowledge of how gates control the electrostatic and dynamic properties of multiqubit devices, the operator can more quickly and easily navigate the multidimensional gate space to find a qubit operating regime. We have developed and applied image analysis techniques to quantitatively detect where charge offsets from different quantum dots intersect, so called anticrossings. In this document we outline the details of our algorithm for detecting single anticrossings, which has been used to fine-tune the inter-dot tunnel rates for a three quantum dot system. Additionally, we show that our algorithm can detect multiple anticrossings in the same dataset, which can aid in the coarse tuning the electron occupation of multiple quantum dots. We also include an application of cross correlation to the imaging of magnetic fields using nitrogen vacancies.
The 2017 Electrical and Electronics Technical Team Roadmap [1] proposes aggressive research and development targets aimed at improving power electronics technology to enable the mass-market penetration of electric-drive vehicles. Achieving these aggressive targets will require a decrease in cost (year 2025 cost target: $2.70/kW) and an increase in power density (year 2025 power density target: 100 kW/L) as compared with current on-road technology. Replacing traditional silicon device-based components with more efficient and higher-temperature wide-bandgap (WBG) semiconductor device-based components will enable increased power density. However, meeting the power density target will also require innovative thermal management solutions to increase the heat fluxes dissipated and allow for compact electronics packaging. This project conducts research to develop new power electronics thermal management technologies to increase power density, enable high WBG temperature operation, and decrease cost. The performance (e.g., thermal resistance, pumping power) of the power electronics cooling technologies developed in this project are compared to the performance of current, on-road technology. One of the main challenges to achieving high power densities is associated with packaging high-temperature (up to 250 degrees C) WBG devices near lower-temperature-rated components (e.g., electrical boards and capacitors).
The 2017 Electrical and Electronics Technical Team Roadmap [1] proposes aggressive research and development targets aimed at improving power electronics technology to enable the mass-market penetration of electric-drive vehicles. Achieving these aggressive targets will require a decrease in cost (year 2025 cost target: $2.70/kW) and an increase in power density (year 2025 power density target: 100 kW/L) as compared with current on-road technology. Replacing traditional silicon device-based components with more efficient and higher-temperature wide-bandgap (WBG) semiconductor device-based components will enable increased power density. However, meeting the power density target will also require innovative thermal management solutions to increase the heat fluxes dissipated and allow for compact electronics packaging.
The 2017 Electrical and Electronics Technical Team Roadmap [11] proposes aggressive research and development targets aimed at improving power electronics technology to enable the mass-market penetration of electric-drive vehicles. Achieving these aggressive targets will require a decrease in cost (year 2025 cost target: $2.70/kW) and an increase in power density (year 2025 power density target: 100 kW/L) as compared with current on-road technology. Replacing traditional silicon device-based components with more efficient and higher-temperature wide-bandgap (WBG) semiconductor device-based components will enable increased power density. However, meeting the power density target will also require innovative thermal management solutions to increase the heat fluxes dissipated and allow for compact electronics packaging. This project evaluates, designs, and develops thermal management strategies that use dielectric fluid (single-phase heat transfer) as coolants.
Gallium nitride (GaN) nanowire arrays on silicon are able to drive the overall water-splitting reaction with up to 3.3% solar-to-hydrogen efficiency. Photochemical charge separation is key to the operation of these devices, but details are difficult to observe experimentally because of the number of components and interfaces. Here, we use surface photovoltage spectroscopy to study charge transfer in i-, n-, and p-GaN nanowire arrays on n+ -Si wafers in the presence and absence of Rh/Cr 2 O 3 co-catalysts. The effect of the space charge layer and sub-bandgap defects on majority and minority carrier transport can be clearly observed, and estimates of the built-in potential of the junctions can be made. Transient illumination of the p-GaN/n + -Si junction generates up to -1.4 V surface photovoltage by carrier separation along the GaN nanowire axis. This process is central to the overall water-splitting function of the n + -Si/p-GaN/Rh/Cr 2 O 3 nanowire array. Overall, these results improve our understanding of photochemical charge transfer and separation in group III–V semiconductor nanostructures for the conversion of solar energy into fuels.
Ferroelectric materials promise exceptional attributes including low power dissipation, fast operational speeds, enhanced endurance, and superior retention to revolutionize information technology. However, the practical application of ferroelectric-semiconductor memory devices has been significantly challenged by the incompatibility of traditional perovskite oxide ferroelectrics with metal-oxide-semiconductor technology. Recent discoveries of ferroelectricity in binary oxides such as Zn 1-x Mg x O and Hf 1-x Zr x O have been a focal point of research in ferroelectric information technology. Here, this work investigates the ferroelectric properties of Zn 1-x Mg x O utilizing automated band excitation piezoresponse force microscopy. This findings reveal the coexistence of two ferroelectric subsystems within Zn 1-x Mg x O. A “fringing-ridge mechanism” of polarization switching is proposed that is characterized by initial lateral expansion of nucleation without significant propagation in depth, contradicting the conventional domain growth process observed in ferroelectrics. This unique polarization dynamics in Zn 1-x Mg x O suggests a new understanding of ferroelectric behavior, contributing to both the fundamental science of ferroelectrics and their application in information technology.
Strongly correlated materials exhibiting phase transitions which can be controlled through external stimuli, such as electric fields, are promising for future computing technologies beyond conventional semiconductor transistors. Devices that take advantage of structural phase transitions have inherent built‐in memory, reminiscent of synapses and neurons, and are thus natural candidates for neuromorphic computing. Of particular interest are phase‐change oxides, which allow for control over the metal‐to‐insulator transition. Here, X‐ray nano‐diffraction structural imaging of micro‐devices fabricated with the archetypal phase‐change material vanadium sesquioxide (V 2 O 3 ) is reported. The devices contain a Ga ion‐irradiated region where the metal‐to‐insulator transition critical temperature is lowered, a useful feature for controlling neuron‐like spiking behavior. Results show that strain, induced by crystal lattice mismatch between the pristine and irradiated material, leads to a suppression of the metal‐to‐insulator‐transition. Suppression occurs within the irradiated region or along its edges, depending on the defect‐distribution and the size of the region. The observed self‐straining effect can extend to other phase‐change oxides and dominate as device dimensions are reduced and become too small to dissipate strain within the irradiated region. The findings are important for phase engineering in phase‐change devices and highlight the necessity to study phase transitions at the nanoscale.
Doping has proven to be a critical tool for enhancing the performance of organic semiconductors in devices like organic light-emitting diodes. However, the challenge in working with high-ionization-energy (IE) organic semiconductors is to find p-dopants with correspondingly high electron affinity (EA) that will improve the conductivity and charge carrier transport in a film. Here, we use an oxidant that has been recently recognized to be a very strong p-type dopant, hexacyano-1,2,3-trimethylene-cyclopropane (CN6-CP). The EA of CN6-CP has been previously estimated via cyclic voltammetry to be 5.87 eV, almost 300 meV higher than other known high-EA organic molecular oxidants. We measure the frontier orbitals of CN6-CP using ultraviolet and inverse photoemission spectroscopy techniques and confirm a high EA value of 5.88 eV in the condensed phase. The introduction of CN6-CP in a film of large-band-gap, large-IE phenyldi(pyren-1-yl)phosphine oxide (POPy 2 ) leads to a significant shift of the Fermi level toward the highest occupied molecular orbital and a 2 orders of magnitude increase in conductivity. Using CN6-CP and n-dopant (pentamethylcyclopentadienyl)(1,3,5-trimethylbenzene)ruthenium (RuCp*Mes)2, we fabricate a POPy 2 -based rectifying p–i–n homojunction diode with a 2.9 V built-in potential. Blue light emission is achieved under forward bias. Furthermore, this effect demonstrates the dopant-enabled hole injection from the CN6-CP-doped layer and electron injection from the (RuCp*Mes) 2 -doped layer in the diode.
The goals of this SETO project (DE-EE0008559, Accelerated Scaling to Rapid Open-Air Fabrication of Durable Perovskite Solar modules) are to address the principal challenges towards the successful commercialization of perovskite solar modules utilizing scalable, high-throughput open-air spray deposition. The successful outcome of the project will provide the foundation of an all open-air spray deposited perovskite solar module with hole transport layer (HTL), perovskite, electron transport layer (ETL), and barrier layer development while establishing a fundamental understanding of perovskite device behavior under accelerated aging conditions. Through this program, we have made significant progress towards a commercializable pathway for perovskites. (1) We’ve demonstrated the successful open-air deposition of perovskite and transport layer materials. These deposition methods were chosen for their inherent scalability, and open-air processing enables a significant reduction in processing costs. These methods are also compatible with high throughputs, demonstrating the fastest perovskite film deposition at these performance levels. (2) Development of a unique all-fiber laser scribing procedure provides a high-performance, low-cost method for further improvements in scalability. (3) Our group has also placed a unique emphasis on device stability. The development of testing standards for perovskite modules is required to thoroughly evaluate potential candidates for commercialization, and we’ve taken inspiration from current industry standards to provide an honest insight into the performance and reliability of our devices. (4) An extensive cost model detailing the specific contributions of each device layer and production component provides the most thorough evaluation of any perovskite technology against conventional silicon and compound semiconductor solar devices. The cost model is a critical advancement that will provide the foundation for evaluating the levelized cost of energy (LCOE) of this technology.