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At least 217 records · Page 12

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NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗

NASA NTRS1987

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of the second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗

NASA NTRS1989

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗

DOE OSTI2021

Localized strain profile in surface electrode array for programmable composite multiferroic devices

In this work, we investigate localized in-plane strains on the microscale, induced by arrays of biased surface electrodes patterned on piezoelectrics. Particular focus is given to the influence that adjacent electrode pairs have on one another to study the impact of densely packed electrode arrays. We present a series of X-ray microdiffraction studies to reveal the spatially resolved micrometer-scale strain distribution. The strain maps with micrometer-scale resolution highlight how the local strain profile in square regions up to 250 x 250 lm 2 in size is affected by the surface electrodes that are patterned on ferroelectric single-crystal [Pb(Mg 1/3 Nb 2/3 )O 3 ] x -[PbTiO 3 ] 1-x . The experimental measurements and simulation results show the influence of electrode pair distance, positioning of the electrode pair, including the angle of placement, and neighboring electrode pair arrangements on the strength and direction of the regional strain. Our findings are relevant to the development of microarchitected strain-mediated multiferroic devices. The electrode arrays could provide array-addressable localized strain control for applications including straintronic memory, probabilistic computing platforms, microwave devices, and magnetic-activated cell sorting platforms.

42 ENGINEERING↗

DOE OSTI2023

Porting the WAVEWATCH III (v6.07) wave action source terms to GPU

Abstract. Surface gravity waves play a critical role in several processes, including mixing, coastal inundation, and surface fluxes. Despite the growing literature on the importance of ocean surface waves, wind–wave processes have traditionally been excluded from Earth system models (ESMs) due to the high computational costs of running spectral wave models. The development of the Next Generation Ocean Model for the DOE’s (Department of Energy) E3SM (Energy Exascale Earth System Model) Project partly focuses on the inclusion of a wave model, WAVEWATCH III (WW3), into E3SM. WW3, which was originally developed for operational wave forecasting, needs to be computationally less expensive before it can be integrated into ESMs. To accomplish this, we take advantage of heterogeneous architectures at DOE leadership computing facilities and the increasing computing power of general-purpose graphics processing units (GPUs). This paper identifies the wave action source terms, W3SRCEMD, as the most computationally intensive module in WW3 and then accelerates them via GPU. Our experiments on two computing platforms, Kodiak (P100 GPU and Intel(R) Xeon(R) central processing unit, CPU, E5-2695 v4) and Summit (V100 GPU and IBM POWER9 CPU) show respective average speedups of 2× and 4× when mapping one Message Passing Interface (MPI) per GPU. An average speedup of 1.4× was achieved using all 42 CPU cores and 6 GPUs on a Summit node (with 7 MPI ranks per GPU). However, the GPU speedup over the 42 CPU cores remains relatively unchanged (∼ 1.3×) even when using 4 MPI ranks per GPU (24 ranks in total) and 3 MPI ranks per GPU (18 ranks in total). This corresponds to a 35 %–40 % decrease in both simulation time and usage of resources. Due to too many local scalars and arrays in the W3SRCEMD subroutine and the huge WW3 memory requirement, GPU performance is currently limited by the data transfer bandwidth between the CPU and the GPU. Ideally, OpenACC routine directives could be used to further improve performance. However, W3SRCEMD would require significant code refactoring to make this possible. We also discuss how the trade-off between the occupancy, register, and latency affects the GPU performance of WW3.

58 GEOSCIENCES↗

NASA NTRS1982

Geology and image processing

Digital image processing for geological applications will be integrated with geographic information systems and data base management systems. While multiband data sets from radar and multispectral scanners will make extreme demands on memory, bus and processor architectures, it is expected that array processors and VLSI/VHSIC dedicated function chips will allow the use of fast Fourier transform and classification algorithms. It is anticipted that, as processor power increases, the weakest link of a processing system will become the analyst who uses it. Human engineering of systems is therefore recommended for the most effective utilization of remotely sensed geologic data.

Daily, M.↗

NASA NTRS1984

Finite element computation on nearest neighbor connected machines

Research aimed at faster, more cost effective parallel machines and algorithms for improving designer productivity with finite element computations is discussed. A set of 8 boards, containing 4 nearest neighbor connected arrays of commercially available floating point chips and substantial memory, are inserted into a commercially available machine. One-tenth Mflop (64 bit operation) processors provide an 89% efficiency when solving the equations arising in a finite element problem for a single variable regular grid of size 40 by 40 by 40. This is approximately 15 to 20 times faster than a much more expensive machine such as a VAX 11/780 used in double precision. The efficiency falls off as faster or more processors are envisaged because communication times become dominant. A novel successive overrelaxation algorithm which uses cyclic reduction in order to permit data transfer and computation to overlap in time is proposed.

Mcaulay, A. D.↗

NASA NTRS1987

Binary synaptic connections based on memory switching in a-Si:H for artificial neural networks

A scheme for nonvolatile associative electronic memory storage with high information storage density is proposed which is based on neural network models and which uses a matrix of two-terminal passive interconnections (synapses). It is noted that the massive parallelism in the architecture would require the ON state of a synaptic connection to be unusually weak (highly resistive). Memory switching using a-Si:H along with ballast resistors patterned from amorphous Ge-metal alloys is investigated for a binary programmable read only memory matrix. The fabrication of a 1600 synapse test array of uniform connection strengths and a-Si:H switching elements is discussed.

Thakoor, A. P.↗

NASA NTRS1999

Nano-Satellite Avionics

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

Culver, Harry↗

DOE OSTI2023

Evaluating Awkward Arrays, uproot, and coffea as a query platform for High Energy Physics Data

Query languages for High Energy Physics (HEP) are an ever present topic within the field. A query language that can efficiently represent the nested data structures that encode the statistical and physical meaning of HEP data will help analysts by ensuring their code is more clear and pertinent. As the result of a multi-year effort to develop an in-memory columnar representation of high energy physics data, the NumPy, Awkward Array, and uproot Python packages present a mature and efficient interface to HEP data. Atop that base, the coffea package adds functionality to launch queries at scale, manage and apply experiment-specific transformations to data, and present a rich object-oriented columnar data representation to the analyst. Recently, a set of Analysis Description Language (ADL) benchmarks has been established to compare HEP queries in multiple languages and frameworks. In this paper we present these benchmark queries implemented within the coffea framework and discuss their readability and performance characteristics. We find that the columnar queries perform as well or better than the implementations given in previous studies.

Gray, L.↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS1983

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Strohkorb, G. A.↗

DOE OSTI2021

Analysis of GPU Data Access Patterns on Complex Geometries for the D3Q19 Lattice Boltzmann Algorithm

GPU performance of the lattice Boltzmann method (LBM) depends heavily on memory access patterns. When implemented with GPUs on complex domains, typically, geometric data is accessed indirectly and lattice data is accessed lexicographically. Although there are a variety of other options, no study has examined the relative efficacy between them. Here, we examine a suite of memory access schemes via empirical testing and performance modeling. We find strong evidence that semi-direct is often better suited than the more common indirect addressing, providing increased computational speed and reducing memory consumption. For the layout, we find that the Collected Structure of Arrays (CSoA) and bundling layouts outperform the common Structure of Array layout; on V100 and P100 devices, CSoA consistently outperforms bundling, however the relationship is more complicated on K40 devices. When compared to state-of-the-art practices, our recommendations lead to speedups of 10–40 percent and reduce memory consumption up to 17 percent. Using performance modeling and computational experimentation, we determine the mechanisms behind the accelerations. We demonstrate that our results hold across multiple GPUs on two leadership class systems, and present the first near-optimal strong results for LBM with arterial geometries run on GPUs.

42 ENGINEERING↗

NASA NTRS1982

Highly versatile computer-controlled television detector system

A description is presented of a television detector system which has been designed to accommodate a wide range of applications. It is currently being developed for use in X-ray diffraction, X-ray astrophysics, and electron microscopy, but it is also well suited for astronomical observations. The image can be integrated in a large, high-speed memory system, in the memory of a computer system, or the target of the TV tube or CCD array. The detector system consists of a continuously scanned, intensified SIT vidicon with scan and processing electronics which generate a digital image that is integrated in the detector memory. Attention is given to details regarding the camera system, scan control and image processing electronics, the memory system, and aspects of detector performance.

Kalata, K.↗

NASA NTRS1994

FFT Computation with Systolic Arrays, A New Architecture

The use of the Cooley-Tukey algorithm for computing the l-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started.

Boriakoff, Valentin↗

NASA NTRS1994

A 500 megabyte/second disk array

Applications at the Army High Performance Computing Research Center's (AHPCRC) Graphic and Visualization Laboratory (GVL) at the University of Minnesota require a tremendous amount of I/O bandwidth and this appetite for data is growing. Silicon Graphics workstations are used to perform the post-processing, visualization, and animation of multi-terabyte size datasets produced by scientific simulations performed of AHPCRC supercomputers. The M.A.X. (Maximum Achievable Xfer) was designed to find the maximum achievable I/O performance of the Silicon Graphics CHALLENGE/Onyx-class machines that run these applications. Running a fully configured Onyx machine with 12-150MHz R4400 processors, 512MB of 8-way interleaved memory, 31 fast/wide SCSI-2 channel each with a Ciprico disk array controller we were able to achieve a maximum sustained transfer rate of 509.8 megabytes per second. However, after analyzing the results it became clear that the true maximum transfer rate is somewhat beyond this figure and we will need to do further testing with more disk array controllers in order to find the true maximum.

Ruwart, Thomas M.↗

NASA NTRS1993

Generating local addresses and communication sets for data-parallel programs

Generating local addresses and communication sets is an important issue in distributed-memory implementations of data-parallel languages such as High Performance Fortran. We show that for an array A affinely aligned to a template that is distributed across p processors with a cyclic(k) distribution, and a computation involving the regular section A, the local memory access sequence for any processor is characterized by a finite state machine of at most k states. We present fast algorithms for computing the essential information about these state machines, and extend the framework to handle multidimensional arrays. We also show how to generate communication sets using the state machine approach. Performance results show that this solution requires very little runtime overhead and acceptable preprocessing time.

Chatterjee, Siddhartha↗

DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗