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At least 217 records · Page 12

Conceptual design of a data reduction system

A telemetry data processing system was defined of the Data Reduction. Data reduction activities in support of the developmental flights of the Space Shuttle were used as references against which requirements are assessed in general terms. A conceptual system design believed to offer significant throughput for the anticipated types of data reduction activities is presented. The design identifies the use of a large, intermediate data store as a key element in a complex of high speed, single purpose processors, each of which performs predesignated, repetitive operations on either raw or partially processed data. The recommended approach to implement the design concept is to adopt an established interface standard and rely heavily on mature or promising technologies which are considered main stream of the integrated circuit industry. The design system concept, is believed to be implementable without reliance on exotic devices and/or operational procedures. Numerical methods were employed to examine the feasibility of digital discrimination of FDM composite signals, and of eliminating line frequency noises in data measurements.

Source record↗

Neural Networks Of VLSI Components

Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

Eberhardt, Silvio P.↗

Photodetector Array For Neural Network

Integrated circuit performs 1,024 threshold operations in parallel. Designed for use in postprocessing output of optical correlator in optoelectronic neural network. Overall function of device to put out digital signals indicative of location(s) of bright spot(s) on detector plane. Response time less than commercial charge-coupled-device (CCD) imaging detector operating at standard television frame rate.

Langenbacher, Harry↗

Practical design of magnetic heading sensors

Although fluxgate magnetometers have been in use for many years, and a number of theoretical studies of these sensors are available, very little information has been published on the engineering choices relating to the detailed design of magnetometers intended for navigational applications in aircraft and other vehicles. This paper addresses some of the problems encountered in the design of the sensing head, the choice of operating mode, and the design of the supporting electronics for a simple low-cost magnetometer system which will produce a digital readout of the magnetic heading of the vehicle in which it is mounted. A major goal of this study has been to develop a design which minimizes circuit complexity, is easy to fabricate and calibrate, and utilizes a minimum of specialized components. Such a magnetometer system is intended either as a stand-alone indicating instrument or as a source of magnetic heading information for a more sophisticated navigational system.

Garner, H. D.↗

High-Voltage-Input Level Translator Using Standard CMOS

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.↗

Optical flip-flops and sequential logic circuits using a liquid crystal light valve

This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.

Fatehi, M. T.↗

Integrated Optoelectronic Interface

Proposed optoelectronic integrated-circuit device serves as "universal" or standard interface for transmission and reception of digital and analog signals in communication, data-processing, and control systems. Eliminates need for custom design of interface circuitry in sense that it embodies "master-chip" design easily adaptable to use with specific equipment. Includes directly modulated semiconductor laser to generate light signals for transmission along optical fiber; positive/intrinsic/negative, avalanche, or other photodiode to detect light signals received along another optical fiber;and driving, synchronizing, preamplifying, and signal-regenerating circuitry. Muliplexes electronic signals before transmission and/or demultiplexes electronic signals after reception.

Katz, Joseph↗

Packet Controller For Wireless Headset

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Christensen, Kurt K.↗

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Source record↗

HunStat – a simple and low-cost potentiostat for analytical and educational purposes

We have developed a truly low-cost (15 USD), simple do-it-yourself (DIY) potentiostat with compact dimensions. The output potential range of this device is between ±1.65 V. The developed instrument takes advantage of a Seeeduino XIAO microcontroller equipped with 10 bit digital-to-analog (D/A) and 12 bit analog-to-digital (A/D) converters and supports various voltammetry techniques, including cyclic voltammetry (CV), differential pulse voltammetry (DPV), and chronoamperometry (CA). Interested users are provided with circuit diagrams, bill of materials, and design files. Additionally, software components are also provided free of charge, including an Arduino sketch and control software. The software enables easy manipulation of electrochemical parameters and visualization of results. The presented design introduces a simple and low-cost DIY potentiostat recommended for both analytical and educational purposes.

47 OTHER INSTRUMENTATION↗

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Adell, Philippe↗

Single-event transient testing of low dropout PNP series linear voltage regulators

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Allen, Gregory↗

Synthesis of Correct Digital Controller Models from Specifications by Model Transformation (21-0320)

The design of high consequence controllers (in weapons systems, autonomy, etc.) that do what they are supposed to do is a significant challenge. Testing simply does not come close to meeting the requirements for assurance. Today circuit designers at Sandia (and elsewhere) typically capture the core behavior of their components using state models in tools such as STATEFLOW. They then check that their models meet certain requirements (e.g. “The system bus must not deadlock” or “both traffic lights at an intersection must not be green at the same time”) using tools called model checkers. If the model checker returns “yes” then the property is guaranteed to be satisfied by the model. However, there are several drawbacks to this industry practice: (1) there is a lot of detail to get right, this is particularly challenging when there are multiple components requiring complex coordination (2) any errors returned by the model checker have to be traced back through the design and fixed, necessitating rework, (3) there are severe scalability problems with this approach, particularly when dealing with concurrency. All this places high demands on the designers who now face not only an accelerated schedule but also controllers of increasing complexity. This report describes a new and fundamentally different approach to the construction of safety-critical digital controllers. Instead of directly constructing a complete model and then trying to verify it, the designer can start with an initial abstract (think “sketch”) model plus the requirements, from which a correct concrete model is automatically synthesized. There is no need for post-hoc verification of required functional properties. Having tool to carry this out will significantly impact the nation’s ability to ensure the safety of high-consequence digital systems. The approach has been implemented in a prototype tool, along with a suite of examples, including ones that reflect actual problems faced by designers. Our approach operates on a variant of Statecharts developed at Sandia called Qspecs. Statecharts are a widely used formalism for developing concurrent reactive systems, supporting scalability through allowing state models containing composite states, which are the serial or parallel composition of substates which can themselves contain statecharts. Statecharts enable an incremental style of development, in which states are progressively refined to incorporate greater detail in an incremental model of software development. Our approach formulates a set of constraints from the structure of the models and the requirements and propagates these constraints to a fixpoint. The solution to the constraints is an inductive invariant along with guards on the transitions. We also show how our approach extends to implementation refinement, decomposition, composition, and elaboration. We currently handle safety requirements written in LTL (Linear Temporal Logic)

42 ENGINEERING↗

A Multi-Mode Blade Damping Control using Shunted Piezoelectric Transducers with Active Feedback Structure

The Structural Dynamics and. Mechanics branch (RXS) is developing smart adaptive structures to improve fan blade damping at resonances using piezoelectric (PE) transducers. In this presentation, only one shunted PE transducer was used to demonstrate active control of multi-mode blade resonance damping on a titanium alloy (Ti-6A1-4V) flat plate model, regardless of bending, torsion, and 2-stripe modes. This work would have a significant impact on the conventional passive shunt damping world because the standard feedback control design tools can now be used to design and implement electric shunt for vibration control. In other words, the passive shunt circuit components using massive inductors and. resistors for multi-mode resonance control can be replaced with digital codes. Furthermore, this active approach with multi patches can simultaneously control several modes in the engine operating range. Dr. Benjamin Choi presented the analytical and experimental results from this work at the Propulsion-Safety and. Affordable Readiness (P-SAR) Conference in March, 2009.

Choi, Benjamin↗

3-D Printed Electro-Magnetic Objects for THz Communications

Advanced materials and manufacturing techniques will pave the path towards high quality electro-magnetic circuits that operate up through THz and into optics regime. Digital additive manufacturing (AM) techniques offer game-changing potential for large scale manufacturing of Radio-frequency (RF) circuits and system in custom 2D/3D geometries. The technical collaboration will explore the design flexibility and product customization capabilities of additive manufacturing techniques to process magnetic materials in custom 3D geometries with tailored dielectric properties and frequency response characteristics. Transformation of an RF circuit design idea into a 3D printed system using additive manufacturing techniques will bring together the elements of advanced materials, additive integration, and low-cost manufacturing for future advanced wireless communication systems.

36 MATERIALS SCIENCE↗

Microprogramed Sequencer for Tunable RF Oscillator

Standard IC chips and digitally tuned oscillator combined. Circuit consists of PROM-based microprogramed control sequencer, which drives group of diode switches to select one of eight tuning capacitors in L-C oscillator. Circuit originally designed to "dither" transmitter frequency of K-band radar at high rates finds application in other areas, as automated test equipment or computer-controlled receiver tuning.

Couch, R. H.↗

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Focal Plane Assembly↗

Fast digital lossy compression for X-ray ptychographic data

Increases in X-ray brightness from synchrotron light sources lead to a requirement for higher frame rates from hybrid pixel array detectors (HPADs), while also favoring charge integration over photon counting. However, transfer of the full uncompressed data will begin to constrain detector design, as well as limit the achievable continuous frame rate. Here a data compression scheme that is easy to implement in a HPAD's application-specific integrated circuit (ASIC) is described, and how different degrees of compression affect image quality in ptychography, a commonly employed coherent imaging method, is examined. Using adaptive encoding quantization, it is shown in simulations that one can digitize signals up to 16383 photons per pixel (corresponding to 14 bits of information) using only 8 or 9 bits for data transfer, with negligible effect on the reconstructed image.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗