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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The Clifford + R gate-set is a promising basis for fault-tolerant synthesis of qutrit unitaries. We present an algorithm for approximating an arbitrary single-qutrit unitary with a circuit over the Clifford + R gates. Moreover, we analyze its complexity and obtain the non-Clifford gates cost.
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Tests were performed to determine the damage to samples of composite material when a current carrying wire is shorted to the surface of the composite material, and to determine whether enough current can flow through the material to blow a fuse before damage can occur. Fault current tests were performed on samples of graphite epoxy materials. Samples consisted of six layers of IM7 graphite fiber mat in Hercules 8552 epoxy resin. A variable power supply provided up to 35 amps of current. The high voltage side of the power supply was attached to a wire at the end of a hinged arm, and the low side was attached to the edge of the sample. To test joints, the return was connected to the edge of one sample, and the high side was shorted to the top of the other sample. Tests show that when current exceeds approximately 5 amps, the graphite glows, and the epoxy melts out at the shorted contact. At higher current levels the epoxy burns. At voltages above 15 volts the epoxy outer coat is easily broken, and fire, flame, and a rise in current occur suddenly. When joints are introduced, resistance is increased, and the maximum current resulting from a short circuit to the graphite epoxy is reduced. This condition can easily result in fault current lower than the circuit breaker limit and higher than the 5 amp ignition level. The shorting contact and the joint become hot spots with melting epoxy, smoke, and fire.
Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024
This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.
Distribution systems are currently facing steep operational challenges as a result of the rapidly increasing integration of renewables and other distributed energy resources (DERs) at both the primary and secondary circuit levels. Distribution utilities and system operators have traditionally had some visibility of their primary circuits using low-frequency supervisory control and data acquisition systems, and they have had very poor if not zero visibility of the secondary circuits where the presence of DERs is constantly increasing. Therefore, this paper presents simulation studies to demonstrate the benefits of an advanced, high-fidelity sensor technology, called as the Meta-Alert System (MAS), developed by Electrical Grid Monitoring, Ltd. (EGM), on the distribution grid. First, a reliable model of the EGM sensors is developed, and then two use cases, distribution system state estimation (DSSE) and fault identification are simulated to evaluate the performance of the MAS technology. Simulation results on the Electric Power Research Institute J1 feeder demonstrate that the MAS can effectively participate in system-level DSSE programs and can detect and locate faults faster than traditional distribution protection schemes.
The short-circuit response of inverter-interfaced distributed generators (IIDGs) is not adequately represented in many conventional protection studies. This paper presents an in-depth analysis of IIDG behavior during grid faults and proposes a more accurate reduced-order parameterized short-circuit current (RPSC) model of inverters. Typical inverter components are thoroughly investigated to identify those that play dominant roles during faults. The paper shows that the current limiter is the dominant factor for the steady-state fault-current of inverter; while the inverter filter along with the severity of the voltage disturbance largely determine the initial transient spike of inverter fault current. The proposed model is low-order and can be used in large scale simulations. The parameters of the proposed RPSC model can be extracted from laboratory experiments without requiring proprietary manufacturer information. The proposed fault-current model is analogous to the well-known synchronous machine model that segregates the inverter fault current into subtransient, transient, and steady-state fault currents. Finally, experimental and simulation tests are presented to validate the model.
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.
Studies were conducted to develop appropriate space shuttle electrical power distribution and control (EPDC) subsystem simulation models and to apply the computer simulations to systems analysis of the EPDC. A previously developed software program (SYSTID) was adapted for this purpose. The following objectives were attained: (1) significant enhancement of the SYSTID time domain simulation software, (2) generation of functionally useful shuttle EPDC element models, and (3) illustrative simulation results in the analysis of EPDC performance, under the conditions of fault, current pulse injection due to lightning, and circuit protection sizing and reaction times.
An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.
Protecting inverter-interfaced microgrids is challenging as conventional time-overcurrent protection becomes unusable due to the lack of fault current. There is a great need for novel protective relaying methods that enable the application of protection coordination on microgrids, thereby allowing for microgrids with larger areas and numbers of loads while not compromising reliable power delivery. Tools for modeling and analyzing such microgrids under fault conditions are necessary in order to help design such protective relaying and operate microgrids in a configuration that can be protected, though there is currently a lack of tools applicable to inverter-interfaced microgrids. This paper introduces the concept of applying an optimization problem formulation to the topic of inverter-interfaced microgrid fault modeling, and discusses how it can be employed both for simulating short-circuits and as a set of constraints for optimal microgrid operation to ensure protective device coordination.
The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.
Health management systems that more accurately and quickly diagnose faults that may occur in different technical systems on-board a vehicle will play a key role in the success of future NASA missions. We discuss in this paper the diagnosis of abrupt continuous (or parametric) faults within the context of probabilistic graphical models, more specifically Bayesian networks that are compiled to arithmetic circuits. This paper extends our previous research, within the same probabilistic setting, on diagnosis of abrupt discrete faults. Our approach and diagnostic algorithm ProDiagnose are domain-independent; however we use an electrical power system testbed called ADAPT as a case study. In one set of ADAPT experiments, performed as part of the 2009 Diagnostic Challenge, our system turned out to have the best performance among all competitors. In a second set of experiments, we show how we have recently further significantly improved the performance of the probabilistic model of ADAPT. While these experiments are obtained for an electrical power system testbed, we believe they can easily be transitioned to real-world systems, thus promising to increase the success of future NASA missions.
This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.
A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.
Unbalanced faults in distribution feeders can impact voltages on the non-faulted phases. This paper models a real-life feeder with a high penetration level of solar photovoltaic (PV) units in detail including the secondary circuits, and shows a large voltage swell in one of the non-faulted phases of the feeder during a single line to ground fault. The voltages seen during this swell are more than 1.2 p.u., which can have detrimental impacts on the connected equipment and can also lead to loss of connected generation. The reason for this voltage swell is found to be the equivalent impedance at the fault location resulting from the ratio of zero and positive sequence cable impedances. It is seen that the connected solar PV units with appropriate control are able to reduce the severity of the voltage swell, especially for higher penetration levels of solar PV considered, but not entirely eliminate it.
We present a hardware-reconfigurable ansatz on N q -qubits for the variational preparation of many-body states of the Anderson impurity model (AIM) with N imp + N bath = N q /2 sites, which conserves total charge and spin z component within each variational search subspace. The many-body ground state of the AIM is determined as the minimum over all minima of O(N$^2_ q$) distinct charge-spin sectors. Hamiltonian expectation values are shown to require ω(N q ) < N meas. $\leqslant$ O(N imp N bath ) symmetry-preserving, parallelizable measurement circuits, each amenable to postselection. To obtain the one-particle impurity Green’s function we show how initial Krylov vectors can be computed via midcircuit measurement and how Lanczos iterations can be computed using the symmetry-preserving ansatz. For a single-impurity Anderson model with a number of bath sites increasing from one to seven, we show using numerical emulation that the ease of variational ground-state preparation is suggestive of linear scaling in circuit depth and subquartic scaling in optimizer complexity. We therefore expect that, combined with time-dependent methods for Green’s function computation, our ansatz provides a useful tool to account for electronic correlations on early fault-tolerant processors. Finally, with a view towards computing real materials properties of interest like magnetic susceptibilities and electron-hole propagators, we provide a straightforward method to compute many-body, time-dependent correlation functions using a combination of time evolution, midcircuit measurement-conditioned operations, and the Hadamard test.