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203 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Coding for Communication Channels with Dead-Time Constraints

Coding schemes have been designed and investigated specifically for optical and electronic data-communication channels in which information is conveyed via pulse-position modulation (PPM) subject to dead-time constraints. These schemes involve the use of error-correcting codes concatenated with codes denoted constrained codes. These codes are decoded using an interactive method. In pulse-position modulation, time is partitioned into frames of Mslots of equal duration. Each frame contains one pulsed slot (all others are non-pulsed). For a given channel, the dead-time constraints are defined as a maximum and a minimum on the allowable time between pulses. For example, if a Q-switched laser is used to transmit the pulses, then the minimum allowable dead time is the time needed to recharge the laser for the next pulse. In the case of bits recorded on a magnetic medium, the minimum allowable time between pulses depends on the recording/playback speed and the minimum distance between pulses needed to prevent interference between adjacent bits during readout. The maximum allowable dead time for a given channel is the maximum time for which it is possible to satisfy the requirement to synchronize slots. In mathematical shorthand, the dead-time constraints for a given channel are represented by the pair of integers (d,k), where d is the minimum allowable number of zeroes between ones and k is the maximum allowable number of zeroes between ones. A system of the type to which the present schemes apply is represented by a binary- input, real-valued-output channel model illustrated in the figure. At the transmitting end, information bits are first encoded by use of an error-correcting code, then further encoded by use of a constrained code. Several constrained codes for channels subject to constraints of (d,infinity) have been investigated theoretically and computationally. The baseline codes chosen for purposes of comparison were simple PPM codes characterized by M-slot PPM frames separated by d-slot dead times.

Moision, Bruce↗
NASA NTRS1998

Co- and/or post-translational modifications are critical for TCH4 XET activity

TCH4 encodes a xyloglucan endotransglycosylase (XET) of Arabidopsis thaliana. XETs endolytically cleave and religate xyloglucan polymers; xyloglucan is one of the primary structural components of the plant cell wall. Therefore, XET function may affect cell shape and plant morphogenesis. To gain insight into the biochemical function of TCH4, we defined structural requirements for optimal XET activity. Recombinant baculoviruses were designed to produce distinct forms of TCH4. TCH4 protein engineered to be synthesized in the cytosol and thus lack normal co- and post-translational modifications is virtually inactive. TCH4 proteins, with and without a polyhistidine tag, that harbor an intact N-terminus are directed to the secretory pathway. Thus, as predicted, the N-terminal region of TCH4 functions as a signal peptide. TCH4 is shown to have at least one disulfide bond as monitored by a mobility shift in SDS-PAGE in the presence of dithiothreitol (DTT). This disulfide bond(s) is essential for full XET activity. TCH4 is glycosylated in vivo; glycosidases that remove N-linked glycosylation eliminated 98% of the XET activity. Thus, co- and/or post-translational modifications are critical for optimal TCH4 XET activity. Furthermore, using site-specific mutagenesis, we demonstrated that the first glutamate residue of the conserved DEIDFEFL motif (E97) is essential for activity. A change to glutamine at this position resulted in an inactive protein; a change to aspartic acid caused protein mislocalization. These data support the hypothesis that, in analogy to Bacillus beta-glucanases, this region may be the active site of XET enzymes.

NASA Discipline Cell Biology↗
NASA NTRS2010

Steerable Hopping Six-Legged Robot

The figure depicts selected aspects of a six-legged robot that moves by hopping and that can be steered in the sense that it can be launched into a hop in a controllable direction. This is a prototype of hopping robots being developed for use in scientific exploration of rough terrain on remote planets that have surface gravitation less than that of Earth. Hopping robots could also be used on Earth, albeit at diminished hopping distances associated with the greater Earth gravitation. The upper end of each leg is connected through two universal joints to an upper and a lower hexagonal frame, such that the tilt of the leg depends on the relative position of the two frames. Two non-back-driveable worm-gear motor drives are used to control the relative position of the two frames along two axes 120 apart, thereby controlling the common tilt of all six legs and thereby, further, controlling the direction of hopping. Each leg includes an upper and a lower aluminum frame segment with a joint between them. A fiberglass spring, connected via hinges to both segments, is used to store hopping energy prior to launch into a hop and to cushion the landing at the end of the hop. A cable for loading the spring is run into each leg through the center of the universal joints and then down along the center lines of the segments to the lower end of the leg. A central spool actuated by a motor with a harmonic drive and an electromagnetic clutch winds in all six cables to compress all six springs (thereby also flexing all six legs) simultaneously. To ensure that all the legs push off and land in the same direction, timing- belt pulley drives are attached to the leg segments, restricting the flexing and extension of all six legs to a common linear motion. In preparation for a hop, the spool can be driven to load the spring legs by an amount corresponding to a desired hop distance within range. The amount of compression can be computed from the reading of a shaft-angle encoder that indicates the amount by which the spool has been turned. When the robot is ready to hop, the electromagnetic clutch disengages the motor from the spool, thus releasing the cable restraints on the springs and allowing the springs to extend all six legs simultaneously.

Younse, Paulo↗
NASA NTRS2012

Ultra-Compact Motor Controller

This invention is an electronically commutated brushless motor controller that incorporates Hall-array sensing in a small, 42-gram package that provides 4096 absolute counts per motor revolution position sensing. The unit is the size of a miniature hockey puck, and is a 44-pin male connector that provides many I/O channels, including CANbus, RS-232 communications, general-purpose analog and digital I/O (GPIO), analog and digital Hall inputs, DC power input (18-90 VDC, 0-l0 A), three-phase motor outputs, and a strain gauge amplifier. This controller replaces air cooling with conduction cooling via a high-thermal-conductivity epoxy casting. A secondary advantage of the relatively good heat conductivity that comes with ultra-small size is that temperature differences within the controller become smaller, so that it is easier to measure the hottest temperature in the controller with fewer temperature sensors, or even one temperature sensor. Another size-sensitive design feature is in the approach to electrical noise immunity. At a very small size, where conduction paths are much shorter than in conventional designs, the ground becomes essentially isopotential, and so certain (space-consuming) electrical noise control components become unnecessary, which helps make small size possible. One winding-current sensor, applied to all of the windings in fast sequence, is smaller and wastes less power than the two or more sensors conventionally used to sense and control winding currents. An unexpected benefit of using only one current sensor is that it actually improves the precision of current control by using the "same" sensors to read each of the three phases. Folding the encoder directly into the controller electronics eliminates a great deal of redundant electronics, packaging, connectors, and hook-up wiring. The reduction of wires and connectors subtracts substantial bulk and eliminates their role in behaving as EMI (electro-magnetic interference) antennas. A shared knowledge by each motor controller of the state of all the motors in the system at 500 Hz also allows parallel processing of higher-level kinematic matrix calculations.

Townsend, William T.↗
NASA NTRS2013

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗