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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Methods for growth of relatively large step-free SiC crystal surfaces

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Neudeck, Philip G.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS1979

Modelling switching-time effects in high-frequency power conditioning networks

Power transistor networks which switch large currents in highly inductive environments are beginning to find application in the hundred kilohertz switching frequency range. Recent developments in the fabrication of metal-oxide-semiconductor field-effect transistors in the power device category have enhanced the movement toward higher switching frequencies. Models for switching devices and of the circuits in which they are imbedded are required to properly characterize the mechanisms responsible for turning on and turning off effects. Easily interpreted results in the form of oscilloscope-like plots assist in understanding the effects of parametric studies using topology oriented computer-aided analysis methods.

Owen, H. A.↗
NASA NTRS1972

Previous design restraints and radiation damage effects of low energy particles

Spacecraft design fluences and damage by low energy electrons and protons are summarized. For electron energies 5 MeV, the design fluence is 10 to the 11th power electrons/sq cm; for energies 5 MeV, the integral spectrum is assumed to go as 1/E sq. The design fluences for proton energies 30 MeV is 1.5 x 10 to the 9th power protons/sq cm; for energies 100 MeV, it is 5 x 10 to the 14th power protons/sq cm. The radioisotope thermoelectric generator gamma and neutron radiation constraints are listed. Damage due to electron energies 0.5 MeV and proton energies 10 MeV are summarized for effects on spacecraft thermal surfaces, reflective surfaces, and refractive materials. The high frequency noise figure for field effect transistors may increase markedly, and another effect is the buildup of charge on insulating surfaces, resulting in large electric fields.

Trainor, J. H.↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRS2007

Fabrication of a Thermally Isolated and Pre-amplified Transistor Module with Polyimide Micro-wires for Cryogenic Detectors

For use in cryogenic applications such as bolometer and x-ray microcalorimeter arrays, pre-amplifying Junction Field Effect Transistors (JFETs) are often required for the readout electronics. The optimum operating temperature of the JFETs is 130 Kelvin while the cryogenic detectors operate in the milli-Kelvin range. Thus, the JFETs must be heated up but thermally isolated from the surrounding cryogenic instruments. In the past, the thermal isolation was accomplished by suspending the JFETs with low conductance wires such as manganium or stainless steel on a Kevlar support platform [I]. This also achieved electrical connections. However, this assembly required manual soldering work, which could raise a reliability issue for the cryogenic applications. In order to eliminate the manual work, polyimide micro-wires were developed [2]. The wires must be of sufficient length to decrease the heat load and in tension to prevent microphonic noise from vibration of the wires: the polyimide wires were patterned into llS"shaped curves over a thin metal wires such as aluminum, titanium, or niobium. The bilayer of the films were then suspended by etching silicon substrate thus to make freestanding air bridges (enough explanation?). In this paper, we present a method to fabricate micromachined JFET mechanical modules suspended by polyimide Pyraline micro-wires and heated up with built-in aluminum micro-heaters.

Oh, L. H.↗
NASA NTRS2008

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

Neudeck, Philip G.↗
NASA NTRS2014

Investigation of the Semicoa 2N7616 and 2N7425 and the Microsemi 2N7480 for Single-Event Gate Rupture and Single-Event Burnout

Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. The 2N7616 and the 2N7425 from Semicoa and the 2N7480 from International Rectifier were tested to NASA test condition standards and requirements. The 2N7480 performed well and the data agree with the manufacture's data. The 2N7616 and 2N7425 were entry parts from Semicoa using a new device architecture. Unfortunately, the device performed poorly and Semicoa is withdrawing power MOSFETs from it line due to these data. Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most commonly used power transistor. MOSFETs are typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single-event gate rupture (SEGR) or single-event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. See [1] through [5] for more information. The objective of this effort was to investigate the SEGR and SEB responses of two power MOSFETs recently produced. These tests will serve as a limited verification of these parts. It is acknowledged that further testing on the respective parts may be needed for some mission profiles.

Scheick, Leif↗
NASA NTRS2012

Radiation and Thermal Cycling Effects on EPC1001 Gallium Nitride Power Transistors

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Information pertaining to performance of electronic parts and systems under hostile environments is very scarce, especially for new devices. Such data is very critical so that proper design is implemented in order to ensure mission success and to mitigate risks associated with exposure of on-board systems to the operational environment. In this work, newly-developed enhancement-mode field effect transistors (FET) based on gallium nitride (GaN) technology were exposed to various particles of ionizing radiation and to long-term thermal cycling over a wide temperature range. Data obtained on control (un-irradiated) and irradiated samples of these power transistors are presented and the results are discussed.

Patterson, Richard L.↗
NASA NTRS2008

Dual-Input AND Gate From Single-Channel Thin-Film FET

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Miranda, F. A.↗
NASA NTRS2010

Static Characteristics of the Ferroelectric Transistor Inverter

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Mitchell, Cody↗
NASA NTRS1993

GaAs-based optoelectronic neurons

An integrated, optoelectronic, variable thresholding neuron implemented monolithically in GaAs integrated circuit and exhibiting high differential optical gain and low power consumption is presented. Two alternative embodiments each comprise an LED monolithically integrated with a detector and two transistors. One of the transistors is responsive to a bias voltage applied to its gate for varying the threshold of the neuron. One embodiment is implemented as an LED monolithically integrated with a double heterojunction bipolar phototransistor (detector) and two metal semiconductor field effect transistors (MESFET's) on a single GaAs substrate and another embodiment is implemented as an LED monolithically integrated with three MESFET's (one of which is an optical FET detector) on a single GaAs substrate. The first noted embodiment exhibits a differential optical gain of 6 and an optical switching energy of 10 pJ. The second embodiment has a differential optical gain of 80 and an optical switching energy of 38 pJ. Power consumption is 2.4 and 1.8 mW, respectively. Input 'light' power needed to turn on the LED is 2 micro-W and 54 nW, respectively. In both embodiments the detector is in series with a biasing MESFET and saturates the other MESFET upon detecting light above a threshold level. The saturated MESFET turns on the LED. Voltage applied to the biasing MESFET gate controls the threshold.

Lin, Steven H.↗
NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗
NASA NTRS1979

Voltage regulator for battery power source

A bipolar transistor in series with the battery as the control element also in series with a zener diode and a resistor is used to maintain a predetermined voltage until the battery voltage decays to very nearly the predetermined voltage. A field effect transistor between the base of the bipolar transistor and a junction between the zener diode and resistor regulates base current of the bipolar transistor, thereby regulating the conductivity of the bipolar transistor for control of the output voltage.

Black, J. M.↗
NASA NTRS2008

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

Neudeck, Philip G.↗
NASA NTRS1978

Preamplifier Noise in VLF Receivers

Noise specifications for junction field-effect transistors are presented in different ways depending on the particular semiconductor manufacturer. Arithmetic involved in converting these specifications to equivalent RMS noise in microvolts developed at the preamplifier input terminal is reviewed. These methods were useful for estimating the noise performance of high input impedance preamplifiers used with E-field antennas operating in the range of 1 KHz to 10 MHz. Both the JFET MPF-102 transistor and the COS/MOS CA3600 transistor array provided amplification for VLF receivers where the internally generated noise was well below the atmospheric noise level. The CA3600 transistor array provided better performance because of the more symmetrical complementary MOS transistor transfer characteristics than a single N-type biased JFET transistor. The CMOS amplifier resulted in self-compensating gain characteristics over a very wide temperature range from -55 to +125 C.

Burhans, R. W.↗
NASA NTRS1989

Characterization of multilayer GaAs/AlGaAs transistor structures by variable angle spectroscopic ellipsometry

Variable angle of incidence spectroscopic ellipsometry (VASE) has been implemented as a means of determining layer thickness, alloy composition, and growth quality of GaAs/AlGaAs samples composed of relatively thick layers as well as superlattices. The structures studied in this work contained GaAs/AlGaAs multilayers with a superlattice 'barrier' and were grown for later formation of modulation-doped field effect transistors (MODFETs). Sample modeling was performed by treating the superlattice as a bulk AlGaAs layer of unknown composition. Extremely good data fits were realized when five layer thicknesses and two alloy ratios were allowed to vary in a regression analysis. Room temperature excitonic effects associated with the e-hh(1), e-lh(1) and e-hh(2) transitions were observed in the VASE data.

Merkel, Kenneth G.↗