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A semiconductor device and methods of fabricating and using the same are provided. The semiconductor device comprises a channel region and at least a first, second, and third electrode. The channel region includes a compound having a transition metal and a chalcogen. The thickness of the channel region is about 3 to about 40 atomic layers.
In an example, the present invention provides a method of forming a semiconductor device on a gallium and nitrogen containing material. The method includes providing a substrate member comprising a surface region, the substrate member comprising a gallium and nitrogen bearing material. The method includes causing an implanted species to electrically activate the implant profile while removing one or more crystalline damage from the epitaxial material to change the amorphous state to a single crystalline state, and thereby creating a substantially electrically activated crystalline material.
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Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.
Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. Data are presented by JPL for various NASA space programs on diodes, bipolar transistors, field effect transistors, silicon-controlled rectifiers, and optical devices. A vendor identification code list is included along with semiconductor device electrical parameter symbols and abbreviations.
Volume 3 of this three-volume set provides a detailed analysis of the data in Volumes 1 and 2, most of which was generated for the Galileo Orbiter Program in support of NASA space programs. Volume 1 includes total ionizing dose radiation test data on diodes, bipolar transistors, field effect transistors, and miscellaneous discrete solid-state devices. Volume 2 includes similar data on integrated circuits and a few large-scale integrated circuits. The data of Volumes 1 and 2 are combined in graphic format in Volume 3 to provide a comparison of radiation sensitivities of devices of a given type and different manufacturer, a comparison of multiple tests for a single data code, a comparison of multiple tests for a single lot, and a comparison of radiation sensitivities vs time (date codes). All data were generated using a steady-state 2.5-MeV electron source (Dynamitron) or a Cobalt-60 gamma ray source. The data that compose Volume 3 represent 26 different device types, 224 tests, and a total of 1040 devices. A comparison of the effects of steady-state electrons and Cobat-60 gamma rays is also presented.
Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.
Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).
Document presents data on and analysis of radiation hardness of various semiconductor devices. Data specifies total-dose radiation tolerance of devices. Volume 1 of report covers diodes, bipolar transistors, field effect transistors, silicon controlled rectifiers and optical devices. Volume 2 covers integrated circuits. Volume 3 provides detailed analysis of data in volumes 1 and 2.
A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.
With NASA Advanced Exploration Systems (AES) Life Support Systems (LSS)baselining ionic silver (Ag+) as the biocide of choice, development in silver monitoring technologies becomes necessary to monitor and control Ag+ release. Ion-selective field effect transistors (ISFETs) and chemically-sensitive field effect transistors (ChemFETs) are capable of selective detection of Ag+ with reversible and low detection limit responses. However, one major hurdle to ChemFET technologies is the requirement of a reference electrode, which can leak its fill solution into the potable water system and is prone to drift requiring frequent calibration. To circumvent this issue, a double chemically-sensitive field effect transistor (dChemFET) is proposed. The dChemFET uses a second ChemFET to selectively monitor the counter ion and serves in place of the reference electrode. This work reports on the development of the dChemFET, starting with the development of the Ag+ andNO3- ion selective membranes (ISMs) to be used in the ChemFETs. The Ag+ ISM was tested in 50-105 ppb Ag+ and showed linear, sub-Nernstian response. The NO3- ISM was tested in50-500 ppb silver ion equivalents of nitrate ion (Ag+ equiv. of NO3-) and shows linear, sub-Nernstian response as well . However, the Ag+ and NO3- ISMs face significant challenges in terms of drift that obstruct its application for long-term monitoring, but it can serve as a starting point for demonstrating the dChemFET proof of concept.
With NASA Advanced Exploration Systems (AES) Life Support Systems (LSS) baselining ionic silver (Ag+) as the biocide of choice, development in silver monitoring technologies becomes necessary to monitor and control Ag+ release. Ion-selctive field effect transistors (ISFETs) and chemically-sensitive field effect transistors (ChemFETs) are capable of selective detection of Ag+ with reversible and low detection limit responses. However, one major hurdle to ChemFET technologies is the requirement of a reference electrode, which can leak its fill solution into the potable water system and is prone to drift requiring frequent calibration. To circumvent this issue, we are developing a double chemically-sensitive field effect transistor (dChemFET). The dChemFET uses a second ChemFET to selectively monitor the counter ion and serves in place of the reference electrode. We report our work in developing the dChemFET, starting with the development of the Ag+ and NO3- ion selective memberanes (ISMs) to be used in the ChemFETs. The Ag+ ISM has a detection range of 50-105 ppb . The counter ion ISM, NO3- ISM, has shown a detection range of 400-105 ppb. NO3- ISMs are limited in detecting at lower ppb levels required for the dChemFET application on the potable water system. In response to this issue, we also report our studies in using the Ag+ ISM to measure deionized (DI) water as a reference measurement to be implemented in-line before the Ag+ is dosed.
Fabrication of high temperature silicon carbide integrated circuit using junction-gate type field effect transistor as active component
A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.
Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.
An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.
Downscaling of the silicon metal-oxide-semiconductor field-effect transistor technology is expected to reach a fundamental limit soon. A paradigm shift in computing is occurring. Spin field-effect transistors are considered a candidate architecture for next-generation microelectronics. Being able to leverage the existing infrastructure for silicon, a spin field-effect transistor technology based on group IV heterostructures will have unparalleled technical and economical advantages. For the same material platform reason, germanium hole quantum dots are also considered a competitive architecture for semiconductor-based quantum technology. In this project, we investigated several approaches to creating hole devices in germanium-based materials as well as injecting hole spins in such structures. We also explored the roles of hole injection in wet chemical etching of germanium. Our main results include the demonstration of germanium metal-oxide-semiconductor field-effect transistors operated at cryogenic temperatures, ohmic current-voltage characteristics in germanium/silicon-germanium heterostructures with ferromagnetic contacts at deep cryogenic temperatures and high magnetic fields, evaluation of the effects of surface preparation on carrier mobility in germanium/silicon- germanium heterostructures, and hole spin polarization through integrated permanent magnets. These results serve as essential components for fabricating next-generation germanium-based devices for microelectronics and quantum systems.
The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.