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In this presentation, we provide a brief glimpse at preliminary single event test results taken from two years of testing of the Xilinx V5QV Field Programmable Gate Array (FPGA). This presentation includes an overview of test philosophy and implementation.
Within this paper, we report on an Optimetrics experiment conducted on the National Aeronautics and Space Administration (NASA) Laser Communication Relay Demonstration (LCRD). The high precision two-way ranging is conducted on the optical communications link between the LCRD space terminal in a geosynchronous orbit and the Optical Ground Station 1 (OGS1) at Table Mountain, California, and is referred to as optimetrics ranging. The receiver to transmitter clock loopback is implemented in the LCRD space modem. A digital dual mixer time difference phase meter (DDMTD) is implemented in the OGS1 ground modem. The round-trip time is measured with the DDMTD by counting the frame and data clock ticks between transmitter and receiver frame synchronization markers for coarse range, and the relative phase of the transmit and receive clock for high precision range. This approach provides coverage for all potential ranges with no ranging ambiguity. The flight modem FPGA code was modified for frame and data clock loopback and the OGS1 FPGA code was modified for the DDMTD phase meter implementation. The experiment team conducted a 36-hour continuous ranging measurement. Preliminary two-way optimetrics ranging data show a noise floor of 3cm (rms). Based on our theoretical noise analysis and ground tests with spare flight modems, we expected one order of magnitude improvement on ranging precision. We are conducting detailed post data processing to identify the differences to further reduce the noise level and formulating an improved implementation approach for future missions. For reference and comparison, traditional Radio Frequency (RF) ranging between LCRD and OGS1 was conducted at the same time and indicates a ranging noise floor of 30cm(rms). Other telemetry and relevant environmental parameters such as weather and atmosphere temperature were also collected for offline data processing. The high precision ranging and range rate measurements from the laser communications data link clock and clock phase are performed simultaneously with continuous optical communication. No extra hardware added to existing system. This high precision optimetrics measurement implementation provides alternative ranging and range rate measurements for orbit determination (OD) and flight dynamics calculations with higher precision. We see significant improvement on OD for navigation upon implementation in future optical communication systems.
For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.
A prototype Output Data Formatter (ODF) for the ESTAR (Electronically Scanned Thinned Array Radiometer) instrument has been designed and tested. It employs programmable logic devices to format and tag correlator data for transmission to Earth. After accepting 170 bits or correlator and error data in parallel, it appends an identification word and then serially passes the data to the Small Explorer Data System (SEDS) for transmission at a maximum rate of greater than 15 Mb/sec. Implemented with two reprogrammable field programmable gate arrays (FPGA's), each contained in a 132-pin plastic pin grid array (PGA) package, the design is cascadeable, fully testable, and low-power.
We have developed a low-power. programmable radio "microreceiver" that combines the functionality of two science instruments: a Relative Ionospheric Opacity Meter (riometer) and a swept-frequency, VTF/HF radio spectrometer. The radio receiver, calibration noise source, data acquisition and processing, and command and control functions are all contained on a single circuit board. This design is suitable for miniaturizing as a complete flight instrument. Several of the subsystems were implemented in a field-programmable gate array (FPGA), including the receiver detector, the control logic, and the data acquisition and processing blocks. Considerable efforts were made to reduce the power consumption of the instrument, and eliminate or minimize RF noise and spurious emissions generated by the receiver's digital circuitry. A prototype instrument was deployed at McMurdo Station, Antarctica, and operated in parallel with a traditional riometer instrument for approximately three weeks. The attached paper (accepted for publication by Radio Science) describes in detail the microreceiver theory of operation, performance specifications and test results.
The Free-Flying Magnetometer (FFM) is an autonomous "sensorcraft" developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy sounding rocket mission. This mission was a collaborative project between the University of New Hampshire, Cornell University and JPL. The science goal of the mission was the study of current filamentation phenomena in the northern auroral region through multipoint measurements of magnetic field. The technical objective of the mission was the proof of concept of the JPL FFM design and the demonstration of an in-situ multipoint measurement technique employing many free-flying spacecraft. Four FFMs were successfully deployed from a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. These hockey-puck-sized (80 mm diameter, 38 mm. height, 250 gram mass) free flyers each carry a miniature 3-axis flux-gate magnetometer that output +/- 2 V signals corresponding to a +/- 60,000 nT measurement range for each axis. The FFM uses a synchronized four-channel Sigma(Delta) Analog-to-Digital Converter (ADC) having a dynamic range of +/- 2.5V and converting at a rate of 279 samples/second/channel. Three channels are used to digitize the magnetometer signals to 17-bit (1.144 nT/bit) resolution. The fourth ADC channel is multiplexed for system monitoring of four temperature sensors and two battery voltages. The FFM also contains two sun sensors, a laser diode which emits a fan-shaped beam, a miniature S-band transmitter for direct communication to the ground station antennas, an ultra-stable Temperature Compensated Crystal Oscillator (TCXO) clock, an integrated data subsystem implemented in a Field-Programmable Gate Array (FPGA), a 4 Mbit Static Random Access Memory (SRAM) for data storage and Lithium Thionyl Chloride batteries for power. Communicating commands to the FFM prior to deployment is achieved with an infrared (IR) link. The FFM IR receiver responds to 9-bit pulse coded signals that are generated by an IR Light Emitting Diode (LED) in the payload for turning FFM power on or off and placing the FFM in a test mode or flight mode. The IR links are also used to synchronize (zero) the clocks onboard all the FFMs through a reset pulse originating from the payload GPS receiver that is issued when the FFMs are in flight mode. The FPGA based data subsystem manages continuous data collection from the four ADC channels and sun sensors, formatting and storing the data to SRAM, and controlling downlink transmission. The transmitter is powered only after a 2547 frame SRAM buffer has been filled (approx. 5 minutes of data). The data is Viterbi encoded and sent to the S-band transmitter via a First-In-First-Out (FIFO) buffer who's output is clocked at 100 bits/second. After the 26-second transmission, the transmitter is turned off to reduce noise coupling to the sensitive magnetometer. The data subsystem control consists of a master state machine that performs data flow management and is interfaced through a prioritized interrupt scheme to state machines that service the ADC, sun sensors and transmitter FIFO. Continuous data collection prevents the missing of data during transmission and provides implicit time tagging of the data acquired by the ADC because of synchronization with the TCXO clock.
The design and development of a fault-tolerant fiber-optic backplane to demonstrate feasibility of such architecture is presented. The simulation results of test cases on the backplane in the advent of induced faults are presented, and the fault recovery capability of the architecture is demonstrated. The architecture was designed, developed, and implemented using the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). The architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple prototype boards.
In this paper, we present two encoding methods for block-circulant LDPC codes. The first is an iterative encoding method based on the erasure decoding algorithm, and the computations required are well organized due to the block-circulant structure of the parity check matrix. The second method uses block-circulant generator matrices, and the encoders are very similar to those for recursive convolutional codes. Some encoders of the second type have been implemented in a small Field Programmable Gate Array (FPGA) and operate at 100 Msymbols/second.
This paper describes a new reconfigurable analog array (RAA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.
This paper describes a new reconfigurable analog array (MA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.
A document presents additional information on the means of implementing a capability for wide tuning of microwave receiver and transmitter frequencies in the development reported in the immediately preceding article, VCO PLL Frequency Synthesizers for Spacecraft Transponders (NPO- 42909). The reference frequency for a PLL-based frequency synthesizer is derived from a numerically controlled oscillator (NCO) implemented in digital logic, such that almost any reference frequency can be derived from a fixed crystal reference oscillator with microhertz precision. The frequency of the NCO is adjusted to track the received signal, then used to create another NCO frequency used to synthesize the transmitted signal coherent with, and at a specified frequency ratio to, the received signal. The frequencies can be changed, even during operation, through suitable digital programming. The NCOs and the related tracking loops and coherent turnaround logic are implemented in a field-programmable gate array (FPGA). The interface between the analog microwave receiver and transmitter circuits and the FPGA includes analog-to-digital and digital-toanalog converters, the sampling rates of which are chosen to minimize spurious signals and otherwise optimize performance. Several mixers and filters are used to properly route various signals.
A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.
A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.
Direct Current (DC) line balanced SpaceWire is attractive for a number of reasons. Firstly, a DC line balanced interface provides the ability to isolate the physical layer with either a transformer or capacitor to achieve higher common mode voltage rejection and or the complete galvanic isolation in the case of a transformer. And secondly, it provides the possibility to reduce the number of conductors and transceivers in the classical SpaceWire interface by half by eliminating the Strobe line. Depending on the modulator scheme the clock data recovery frequency requirements may be only twice that of the transmit clock, or even match the transmit clock: depending on the Field Programmable Gate Array (FPGA) decoder design. In this paper, several different implementation scenarios will be discussed. Two of these scenarios are backward compatible with the existing SpaceWire hardware standards except for changes at the character level. Three other scenarios, while decreasing by half the standard SpaceWire hardware components, will require changes at both the character and signal levels and work with fixed rates. Other scenarios with variable data rates will require an additional SpaceWire interface handshake initialization sequence.
Direct Current (DC) line balanced SpaceWire is attractive for a number of reasons. Firstly, a DC line balanced interface provides the ability to isolate the physical layer with either a transformer or capacitor to achieve higher common mode voltage rejection and/or the complete galvanic isolation in the case of a transformer. Secondly, it provides the possibility to reduce the number of conductors and transceivers in the classical SpaceWire interface by half by eliminating the Strobe line. Depending on the modulator scheme - the clock data recovery frequency requirements may be only twice that of the transmit clock, or even match the transmit clock: depending on the Field Programmable Gate Array (FPGA) decoder design. In this paper, several different implementation scenarios will be discussed. Two of these scenarios are backward compatible with the existing SpaceWire hardware standards except for changes at the character level. Three other scenarios, while decreasing by half the standard SpaceWire hardware components, will require changes at both the character and signal levels and work with fixed rates. Other scenarios with variable data rates will require an additional SpaceWire interface handshake initialization sequence.
A prototype Walsh Function Generator (WFG) for the ESTAR (Electronically Scanned Thinned Array Radiometer) instrument has been designed and tested. Implemented in a single Xilinx XC3020PC68-50 Field Programmable Gate Array (FPGA), it generates a user-programmable set of 32 consecutive Walsh Functions for noise cancellation in the analog circuitry of the Front-End Modules (FEM's). It is implemented in a 68-pin plastic leaded chip carrier (PLCC) package, is fully testable, and can be used for noise cancellation periods as small as 2 msec.
A low cost, low power, and low mass GNSS receiver (called Cion) has been developed and is currently flying on the CICERO cubesats. The receiver was designed in less than a year by JPL for Tyvak and GeoOptics for use in the GeoOptics CICERO constellation and leverages 25 years of JPL GNSS reciever design experience. Cion uses a commercial off-the-shelf (COTS) computer along with existing space qualified RF down-converters, software, and firmware to produce atmospheric Radio Occultation (RO) data. By combining a FPGA with dual core ARM processor and an embedded system controller, the Xilinx Zynq processor is an enabling technology that provides a customizable digital signal processing platform integrated into the computer (System on a chip) and enables off-the-shelf hardware to become the main engine behind this software defined radio. Using Linux for the on-board computer allows for fast development times and liberal use of existing open source software libraries. The parts of the receiver that require realtime implementation are performed in the Field Programmable Gate Array (FPGA), which can also be reprogrammed in flight. While the Zynq is not rad hard, the silicon on insulator (SOI) technology is rad tolerant ‘by accident’, allowing for its use in many space-based applications. Early results show that the Cion is working as designed, has demonstrated the first known GLONASS occultations, and obtains high quality atmospheric profiles with excellent lower troposphere penetration (near Earth’s surface).
One of the main heritage tools used in scientific and engineering data spectrum analysis is the Fourier Integral Transform and its high performance digital equivalent - the Fast Fourier Transform (FFT). The FFT is particularly useful in two-dimensional (2-D) image processing (FFT2) within optical systems control. However, timing constraints of a fast optics closed control loop would require a supercomputer to run the software implementation of the FFT2 and its inverse, as well as other image processing representative algorithm, such as numerical image folding and fringe feature extraction. A laboratory supercomputer is not always available even for ground operations and is not feasible for a night project. However, the computationally intensive algorithms still warrant alternative implementation using reconfigurable computing technologies (RC) such as Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), which provide low cost compact super-computing capabilities. We present a new RC hardware implementation and utilization architecture that significantly reduces the computational complexity of a few basic image-processing algorithm, such as FFT2, image folding and phase diversity for the NASA Solar Viewing Interferometer Prototype (SVIP) using a cluster of DSPs and FPGAs. The DSP cluster utilization architecture also assures avoidance of a single point of failure, while using commercially available hardware. This, combined with the control algorithms pre-hardware optimization, or the first time allows construction of image-based 800 Hertz (Hz) optics closed control loops on-board a spacecraft, based on the SVIP ground instrument. That spacecraft is the proposed Earth Atmosphere Solar Occultation Imager (EASI) to study greenhouse gases CO2, C2H, H2O, O3, O2, N2O from Lagrange-2 point in space. This paper provides an advanced insight into a new type of science capabilities for future space exploration missions based on on-board image processing for control and for robotics missions using vision sensors. It presents a top-level description of technologies required for the design and construction of SVIP and EASI and to advance the spatial-spectral imaging and large-scale space interferometry science and engineering.