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214 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Primitive quantum gates for an S U ( 2 ) discrete subgroup: Binary octahedral

We construct a primitive gate set for the digital quantum simulation of the 48-element binary octahedral ( BO ) group. This non-Abelian discrete group better approximates S U ( 2 ) lattice gauge theory than previous work on the binary tetrahedral group at the cost of one additional qubit—for a total of six—per gauge link. The necessary primitives are the inversion gate, the group multiplication gate, the trace gate, and the BO Fourier transform. Published by the American Physical Society 2024

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Protonic nickelate device networks for spatiotemporal neuromorphic computing

Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.

Electrical and electronic engineering↗
DOE OSTI2020

Real-time dynamic wavelength tuning and intensity modulation of metal-clad nanolasers

To realize ubiquitously used photonic integrated circuits, on-chip nanoscale sources are essential components. Subwavelength nanolasers, especially those based on a metal-clad design, already possess many desirable attributes for an on-chip source such as low thresholds, room-temperature operation and ultra-small footprints accompanied by electromagnetic isolation at pitch sizes down to ∼50 nm. Another valuable characteristic for a source would be control over its emission wavelength and intensity in real-time. Most efforts on tuning/modulation thus far report static changes based on irreversible techniques not suited for high-speed operation. In this study, we demonstrate in-situ dynamical tuning of the emission wavelength of a metallo-dielectric nanolaser at room temperature by applying an external DC electric field. Using an AC electric field, we show that it is also possible to modulate the output intensity of the nanolaser at high speeds. The nanolaser’s emission wavelength in the telecom band can be altered by as much as 8.35 nm with a tuning sensitivity of ∼1.01 nm/V. Additionally, the output intensity can be attenuated by up to 89%, a contrast sufficient for digital data communication purposes. Finally, we achieve an intensity modulation speed up to 400 MHz, limited only by the photodetector bandwidth used in this study, which underlines the capability of high-speed operation via this method. This is the first demonstration of a telecom band nanolaser source with dynamic spectral tuning and intensity modulation based on an external E-field to the best of our knowledge.

Deka, Suruj S. (ORCID:0000000297812317)↗
DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Primitive quantum gates for an S U ( 3 ) discrete subgroup: Σ ( 36 × 3 )

We construct the primitive gate set for the digital quantum simulation of the 108-element Σ ( 36 × 3 ) group. This is the first time a non-Abelian crystal-like subgroup of S U ( 3 ) has been constructed for quantum simulation. The gauge link registers and necessary primitives—the inversion gate, the group multiplication gate, the trace gate, and the Σ ( 36 × 3 ) Fourier transform—are presented for both an eight-qubit encoding and a heterogeneous three-qutrit plus two-qubit register. For the latter, a specialized compiler was developed for decomposing arbitrary unitaries onto this architecture. Published by the American Physical Society 2024

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Organismic materials for beyond von Neumann machines

The elementary basis of intelligence in organisms with a central nervous system includes neurons and synapses and their complex interconnections forming neural circuits. In non-neural organisms such as slime mold with gel-like media, viscosity modulation enables adaptation to changing environments. At a larger scale, collective intelligence emerges via social interactions and feedback in animal colonies. Learning and memory are therefore multi-scale features that evolve as a result of constant interactions with the environment. There is growing interest in emulating such features of intelligence in computing machines and autonomous systems. Materials that can respond to their environment in a manner similar to organisms (referred to as "organismic materials") therefore may be of interest as hardware components in artificial intelligence machines. In this brief review, we present a class of semiconductors called correlated oxides as candidates for learning machines. The term "correlated" refers to the fact that electrons in such lattices strongly interact and the ground state is not what is predicted by classical band theory. Such materials can undergo insulator-metal transitions at near ambient conditions under external stimuli such as thermal or electrical fields, strain, and chemical doping. Depending on the mechanism driving the transition, intermediate states can be metastable with different volatilities, and the time scales of phase change can be controlled over many orders of magnitude. The change in electronic properties can be sharp or gradual, leading to digital or analog behavior. These properties enable the realization of artificial neurons and synapses and emulate the associative and non-associative learning characteristics found in various organisms. We examine microscopic properties concerning electronic and structural transitions leading to collective behavior and theoretical treatments of the ground state and dynamical response, showcasing VO 2 as a model system. Next, we briefly review algorithms designed from the plasticity demonstrated by phase changing systems. Finally, we conclude the brief review with suggestions for future research toward realizing non-von Neumann machines.

42 ENGINEERING↗
DOE OSTI2021

Nanosecond Gated CMOS Camera (NSGCC) ICD (Rev. 2.1)

The Ultra-Fast X-ray Imager (UXI) program is an ongoing effort at Sandia National Laboratories to create high speed, multi-frame, time-gated Read Out Integrated Circuits (ROICs), and a corresponding suite of photodetectors to image a wide variety of High Energy Density (HED) physics experiments on both Sandia’s Z-Machine and LLNL’s National Ignition Facility (NIF). Several cameras have been designed over the length of the program; one of the most recent is the Icarus, which is an improvement on past imagers (Furi and Hippogriff). A second sensor that can be connected is the Daedalus sensor. The Icarus is a 1024 × 512-pixel array with either 25 μm or 8 µm spatial resolution containing four frames of storage per pixel and has improved timing generation and distribution components while achieved 2 ns time gating. The Daedalus sensor is also a 1024 x 512-pixel array with 25 µm special resolution containing three frames of storage per pixel and has an increased set of features for a wider variety of applications from interlacing of rows in each frame to configurability of all shutters. See Section 14 for details regarding the Icarus implementation of the firmware and Section 15 for details regarding the Daedalus implementation. Due to the unique test environments UXI sensors are targeted for, full custom hardware was required to physically mount an Icarus or Daedalus sensor, manage its various functions, and read out pixel data for transfer to a host computer. Beyond experimental functionality, the hardware also needed to accommodate sensor characterization requirements. Lawrence Livermore National Laboratory’s ‘Version 4.0 Board’ was the result of these efforts. It mounts all the components required to fully utilize the Icarus and Daedalus sensors including analog to digital converters to convert pixel data and various system voltages to digital form for readout and analysis, DAC channels for remote configuration of critical bias voltages, static random-access memories to buffer pixel data, RS422 and Gigabit Ethernet communications for remote access, and an FPGA to tie these components together. This document describes the FPGA electrical interfaces in detail to allow the reader a greater understanding of the device, and to facilitate implementation of custom software to control and manage it. The Version 4.0 Board is a continuation of the Nano-second Gated CMOS hardware design that retains much of the functionality of the Version 1.0 Board while adding features including a DAC instead of digital potentiometers, as well as sensors for pressure and radiation. The Version 4.0 board is intended for applications requiring tight form-factor enclosures. It is composed of two stacking boards; one holds the FPGA and regulators to power the various components of the board while the other contains the mating connector to the sensor, image-readoff ADCs, the DAC, and other components.

42 ENGINEERING↗
DOE OSTI2022

The ultrafast pixel array camera system and its applications in high energy density physics

Diagnostics in high energy density physics, shock physics, and related fields are primarily driven by a need to record rapidly time-evolving signals in single-shot events. These measurements are often limited by channel count and signal degradation issues on cable links between the detector and digitizer. Here we present the Ultrafast Pixel Array Camera (UPAC), a compact and flexible detector readout system with 32 waveform-recording channels at up to 10 Gsample/s and 1.8 GHz analog bandwidth. The compact footprint allows the UPAC to be directly embedded in the detector environment. A key enabling technology is the PSEC4A chip, an eight-channel switch-capacitor array sampling device with up to 1056 samples/channel. The UPAC system includes a high-density input connector that can plug directly into an application-specific detector board, programmable control, and serial readout, with less than 5 W of power consumption in full operation. We present the UPAC design and characterization, including a measured timing resolution of ~20 ps or better on acquisitions of sub-nanosecond pulses with minimal system calibrations. Example applications of the UPAC are also shown to demonstrate operation of a solid-state streak camera, an ultrafast imaging array, and a neutron time-of-flight spectrometer.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Electric and Hydraulic Propel Torque Modulation for a Compact Track Loader With the Hybrid Hydraulic Electric Architecture (HHEA)

Abstract The Hybrid Hydraulic Electric Architecture (HHEA) has previously been proposed for off-highway vehicles to reap the efficiency and controllability benefits of electrification without needing very large electric motors. This is achieved with the use of a set of selectable common pressure rails to transmit the majority of power and small electric motors to modulate that power. Previous work has shown significant energy savings for the work circuits of a variety of machines. In this paper, the energy saving potential of HHEA for the propel circuit of a compact track loader is studied. The ports of the track hydraulic motors are selectably connected to the common pressure rails, and instead of using the electric assist motors to buck/boost pressure, as in HHEA for linear actuators, small electric assist motors are used to add/subtract torque directly. The interplay between the torque limits of the electric motors and the ability of the hydraulic motor to vary displacements is studied, along with the effect these factors have on energy saving potential. It is found that the ability to vary the displacement of the hydraulic motor allows for: more efficient electric motor operating conditions, reduced electric torque requirement, and reduced pressure rail switching events. All three of these advantages can be achieved at once using variable displacements; but trade-offs exist between these advantages (i.e. improved efficiency can be achieved at the expense of a larger electric torque requirement). Overall, the HHEA can reduce energy consumption by ∼ 36% compared to the stock machine, depending on the hydraulic motor’s ability to vary displacements, and assuming the electric motor torque is limited to 20% of that required in a direct electrification scheme.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

First operation of a multi-channel Q-Pix prototype: measuring transverse electron diffusion in a gas time projection chamber

We report measurements of the transverse diffusion of electrons in P-10 gas (90% Ar, 10% CH 4 ) in a laboratory-scale time projection chamber (TPC) utilizing a novel pixelated signal capture and digitization technique known as Q-Pix. The Q-Pix method incorporates a precision switched integrating transimpedance amplifier whose output is compared to a threshold voltage. Upon reaching the threshold, a comparator sends a 'reset' signal, initiating a discharge of the integrating capacitor. The time difference between successive resets is inversely proportional to the average current at the pixel in that time interval, and the number of resets is directly proportional to the total collected charge. We developed a 16-channel Q-Pix prototype fabricated from commercial off-the-shelf components and coupled them to 16 concentric annular anode electrodes to measure the spatial extent of the electron swarm that reaches the anode after drifting through the uniform field of the TPC. The swarm is produced at a gold photocathode using pulsed UV light. The measured transverse diffusion agrees with simulations in PyBoltz across a range of operating pressures (200–1500 Torr). These results demonstrate that a Q-Pix readout can successfully reconstruct the ionization topology in a TPC.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

The Majorana Demonstrator readout electronics system

The M AJORANA D EMONSTRATOR comprises two arrays of high-purity germanium detectors constructed to search for neutrinoless double-beta decay in 76 Ge and other physics beyond the Standard Model. Its readout electronics were designed to have low electronic noise, and radioactive backgrounds were minimized by using low-mass components and low-radioactivity materials near the detectors. This paper provides a description of all components of the M AJORANA D EMONSTRATOR readout electronics, spanning the front-end electronics and internal cabling, back-end electronics, digitizer, and power supplies, along with the grounding scheme. The spectroscopic performance achieved with these readout electronics is also demonstrated.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2026

Variational Optical Phase Learning on a Continuous-Variable Quantum Compiler

Quantum process learning is a fundamental primitive that draws inspiration from machine learning with the goal of better studying the dynamics of quantum systems. One approach to quantum process learning is quantum compilation, whereby an analog quantum operation is digitized by compiling it into a series of basic gates. While there has been significant focus on quantum compiling for discrete-variable systems, the continuous-variable (CV) framework has received comparatively less attention. We present an experimental implementation of a CV quantum compiler that uses two-mode squeezed light to learn a Gaussian unitary operation. We demonstrate the compiler by learning a parameterized linear phase unitary through the use of target and control phase unitaries to demonstrate a factor of 5.4 increase in the precision of the phase estimation and a 3.6-fold acceleration in the time-to-solution metric when leveraging quantum resources. We further show how our approach can be extended to higher-dimensional compilation tasks. Our results are enabled by the tunable control of our cost landscape via variable squeezing, thus providing a critical framework to simultaneously increase precision and reduce time-to-solution.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗
DOE OSTI2021

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗