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An analog to digital converter circuit arrangement is reported that is suitable for use in ultra fast pulse height analysis. The circuit uses series connected tunnel diodes to quantize a voltage signal into discrete levels.
Description of a 40-megabit-per-second hard decision sequential decoder which employs the fastest commercially available digital integrated circuits - MECL III. With this decoder an internal computational rate of 70,000,000 computations per second has been achieved. The computational efficiency of the decoding algorithm has been improved by incorporating two modifications to the Fano algorithm - namely, 'double quick threshold loosening' and 'diagonal steps.' On the basis of preliminary results, an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 megabits per second. The very high internal operating speed of the decoder represents a factor of five increase in speed over any previous sequential decoder.
Description of a 40-Mbps hard-decision sequential decoder for high-data-rate coding systems for earth-orbiting space missions with power-limited links. A prototype decoder has been designed and fabricated using the fastest commercially available digital integrated circuits, MECL III. Thus far, an internal computational rate of 70 million computations per second has been achieved. Computational efficiency of the decoding algorithm was greatly improved by incorporating two modifications to the Fano algorithm - 'double quick threshold loosening' and 'diagonal steps.' Preliminary results indicate that an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 Mbps. At lower data rates, even less signal energy is required. This decoder is believed to be at least five times faster than any previous sequential decoder.
To provide data with long-term stability and accuracy, the pulse amplitude modulation (PAM) decommutator was synchronized to the PAM-return to zero wavetrain, and each channel was sampled with a common sample and hold circuit and digitized sequentially. The digital value of each channel was then scaled by the digital value of the calibration channels. The corrected digital value of each channel was stored for one complete frame and then transferred to the multiplexer-demultiplexer at a high rate in one block of serial digital data. A test model was built to demonstrate this design approach taken for the PAM decom and performance data was provided. The accuracies obtained with various signal to noise ratios are shown.
Consisting of NAND gates, switch can be expanded to multipole input and can switch at frequencies up to 30MHz. Device uses digital integrated circuits to provide isolation between inputs and between input and output ports.
Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.
Very high Q digital filtering circuits for audio frequencies in the range of 1Hz to 15 KHz are implemented in simple CMOS hardware using a binary local reference clock frequency. The circuits have application to VLF navigation receivers and other narrow band audio range tracking problems.
A hydrogen gas sensor that can replace catalytic combustion sensors used to detect leaks in the liquid hydrogen transfer systems at Kennedy Space Center was developed. A fluidic sensor concept, based on the principle that the frequency of a fluidic oscillator is proportional to the square root of the molecular weight of its operating fluid, was utilized. To minimize sensitivity to pressure and temperature fluctuations, and to make the sensor specific for hydrogen, two oscillators are used. One oscillator operates on sample gas containing hydrogen, while the other operates on sample gas with the hydrogen converted to steam. The conversion is accomplished with a small catalytic converter. The frequency difference is taken, and the hydrogen concentration computed with a simple digital processing circuit. The output from the sensor is an analog signal proportional to hydrogen content. The sensor is shown to be accurate and insensitive to severe environmental disturbances. It is also specific for hydrogen, even with large helium concentrations in the sample gas.
APSM (Automated Power System Management) is a technology readiness program underway to develop, evaluate, and demonstrate various techniques involved in power system monitoring, as well as computational and control functions. The demonstration breadboard consists of the Viking Orbiter '75 power subassembly breadboard modified to incorporate dedicated microprocessors and digital interface circuits, as well as test support equipment for both spacecraft and ground computer simulation, fault simulation, and data acquisition.
A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.
Components required for extensions of currently planned space communications systems are discussed for large antennas, crosslink systems, single sideband systems, Aerostat systems, and digital signal processing. Systems using advanced modulation concepts and new concepts in communications satellites are included. The current status and trends in materials technology are examined with emphasis on bulk growth of semi-insulating GaAs and InP, epitaxial growth, and ion implantation. Microwave solid state discrete active devices, multigigabit rate GaAs digital integrated circuits, microwave integrated circuits, and the exploratory development of GaInAs devices, heterojunction devices, and quasi-ballistic devices is considered. Competing technologies such as RF power generation, filter structures, and microwave circuit fabrication are discussed. The fundamental limits of semiconductor devices and problems in implementation are explored.
The present invention is a system for deriving direct digital indications of frequency and phase difference between two incoming pulse trains adaptable for collision avoidance systems or the like. A pair of radar beams are directed toward a target and corresponding beams returning therefrom are detected. A digital difference circuit forms a pulse train from the Doppler shift frequencies of each beam pair having a repetition rate functionally related to the difference in magnitude of the shift frequencies. Pulses from the pulse train are counted as a function of time. Visual indications thereof on display are correlative to target position relative to beams.
The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.
The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.
Upper bounds on rates of single-event upsets (SEU's) in digital integrated circuits and other electronic devices exposed to anisotropic fluxes of energetic ionizing particles computed by use of improved method. Derived from simplified, worst-case mathematical models of charge-collecting volumes and physical phenomena in electronic devices.
Digital repeater circuit designed to extend range of communication on MIL-STD-1553 bus beyond original maximum allowable length of 300 ft. Circuit provides two-way communication, one way at time, and conforms to specifications of MIL-STD-1553. Crosstalk and instability eliminated.
Accurate computer simulation of high speed digital computer circuits and communication circuits requires a multimode approach to simulate both the devices and the interconnects between devices. Classical circuit analysis algorithms (lumped parameter) are needed for circuit devices and the network formed by the interconnected devices. The interconnects, however, have to be modeled as transmission lines which incorporate electromagnetic field analysis. An approach to writing a multimode simulator is to take an existing software package which performs either lumped parameter analysis or field analysis and add the missing type of analysis routines to the package. In this work a traditionally lumped parameter simulator, SPICE, is modified so that it will perform lossy transmission line analysis using a different model approach. Modifying SPICE3E2 or any other large software package is not a trivial task. An understanding of the programming conventions used, simulation software, and simulation algorithms is required. This thesis was written to clarify the procedure for installing a device into SPICE3E2. The installation of three devices is documented and the installations of the first two provide a foundation for installation of the lossy line which is the third device. The details of discussions are specific to SPICE, but the concepts will be helpful when performing installations into other circuit analysis packages.
Report presents test data on susceptibility of new set of digital integrated circuits and other semiconductor products to single-event effects (soft errors and latchups) caused by heavy ions incident at high energies. Data used to develop generalizations for protecting electronic equipment from single-event effects. In some cases, tested parts selected as candidates for use in specific applications.