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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

NASA Tech Briefs, June 2007

Topics covered include: High-Accuracy, High-Dynamic-Range Phase-Measurement System; Simple, Compact, Safe Impact Tester; Multi-Antenna Radar Systems for Doppler Rain Measurements; 600-GHz Electronically Tunable Vector Measurement System; Modular Architecture for the Measurement of Space Radiation; VLSI Design of a Turbo Decoder; Architecture of an Autonomous Radio Receiver; Improved On-Chip Measurement of Delay in an FPGA or ASIC; Resource Selection and Ranking; Accident/Mishap Investigation System; Simplified Identification of mRNA or DNA in Whole Cells; Printed Multi-Turn Loop Antennas for RF Biotelemetry; Making Ternary Quantum Dots From Single-Source Precursors; Improved Single-Source Precursors for Solar-Cell Absorbers; Spray CVD for Making Solar-Cell Absorber Layers; Glass/BNNT Composite for Sealing Solid Oxide Fuel Cells; A Method of Assembling Compact Coherent Fiber-Optic Bundles; Manufacturing Diamond Under Very High Pressure; Ring-Resonator/Sol-Gel Interferometric Immunosensor; Compact Fuel-Cell System Would Consume Neat Methanol; Algorithm Would Enable Robots to Solve Problems Creatively; Hypothetical Scenario Generator for Fault-Tolerant Diagnosis; Smart Data Node in the Sky; Pseudo-Waypoint Guidance for Proximity Spacecraft Maneuvers; Update on Controlling Herds of Cooperative Robots; and Simulation and Testing of Maneuvering of a Planetary Rover.

Source record↗
NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [William Rainey Harper Coll.]↗
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗
NASA NTRS2004

A Low Cost Single Chip VDL Compatible Transceiver ASIC

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Becker, Robert↗
DOE OSTI2018

Characterisation and testing of CHEC-M—A camera prototype for the small-sized telescopes of the Cherenkov telescope array

The Compact High Energy Camera (CHEC) is a camera design for the Small-Sized Telescopes (SSTs; 4 m diameter mirror) of the Cherenkov Telescope Array (CTA). The SSTs are focused on very-high-energy γ-ray detection via atmospheric Cherenkov light detection over a very large area. This implies many individual units and hence cost-effective implementation, as well as shower detection at large impact distance, and hence large field of view (FoV), and efficient image capture in the presence of large time gradients in the shower image detected by the camera. CHEC relies on dual-mirror optics to reduce the plate-scale and make use of 6 x 6 mm 2 pixels, leading to a low-cost (~150 k€), compact (0.5 m x 0.5 m), and light (~45 kg) camera with 2048 pixels providing a camera FoV of ~9 degrees. The CHEC electronics are based on custom TARGET (TeV array readout with GSa/s sampling and event trigger) application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) sampling incoming signals at a gigasample per second, with flexible camera-level triggering within a single backplane FPGA. CHEC is designed to observe in the γ-ray energy range of 1–300 TeV, and at impact distances up to 500 m. To accommodate this and provide full flexibility for later data analysis, full waveforms with 96 samples for all 2048 pixels can be read out at rates up to ~900 Hz. The first prototype, CHEC-M, based on multi-anode photomultipliers (MAPMs) as photosensors, was commissioned and characterised in the laboratory and during two measurement campaigns on a telescope structure at the Paris Observatory in Meudon. Here in this paper, the results and conclusions from the laboratory and on-site testing of CHEC-M are presented. They have provided essential input on the system design and on operational and data analysis procedures for a camera of this type. In conclusion, a second full-camera prototype based on Silicon photomultipliers (SiPMs), addressing the drawbacks of CHEC-M identified during the first prototype phase, has already been built and is currently being commissioned and tested in the laboratory.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Thermal Studies of CMS High-Granularity Calorimeter (HGCAL) Cassettes for the HL-LHC Upgrade

The CMS High Granularity Calorimeter (HGCAL) is a key endcap upgrade for the High-Luminosity LHC, designed to operate in an environment of extreme radiation and high particle rates. Each HGCAL cassette integrates silicon and scintillator modules, front-end ASICs, and a copper cooling plate that provides both mechanical integrity and thermal coupling using two-phase CO₂ cooling. Stable and uniform temperature control is essential to ensure reliable performance of the front-end electronics and to limit radiation-induced leakage currents in the silicon sensors. We present results from thermal characterization studies of pre-series HGCAL cassettes assembled and tested at Fermilab. Embedded RTD/PT1000 temperature sensors were used to measure gradients across copper cooling plates, module layers, and cassette edges under powering conditions representative of operation. The measured thermal behavior demonstrates effective heat transport through the cassette stack and highlights small but systematic variations correlated with geometry and assembly tolerances. These results validate the cooling performance of HGCAL cassettes.

Wang, Jinglu [Northwestern U.]↗
DOE OSTI2024

Design and construction of the CMS Outer Tracker for the Phase-2 Upgrade

The High Luminosity LHC (HL-LHC) is expected to deliver an integrated luminosity of $3000-4000\;$fb$^{-1}$ after 10 years of operation with peak instantaneous luminosity reaching about $5-7.5\times10^{34}$cm$^{-2}$s$^{-1}$. During Long Shutdown 3, several components of the CMS detector will undergo major changes, called Phase-2 upgrades, to be able to operate in the challenging environment of the HL-LHC. The current CMS silicon strip tracker has to be replaced with a new detector. The Phase-2 Outer Tracker (OT) will have high radiation tolerance, higher granularity and the capability to handle higher data rates. Another key feature of the OT will be to provide tracking information to the Level-1 trigger, allowing trigger rates to be kept at a sustainable level without sacrificing physics potential. For this, the OT will be made out of modules which have two closely spaced sensors read out by front-end ASICs, which can correlate hits in the two sensors creating short track segments, called stubs. The stubs will be used for tracking in the L1 track finder. In this contribution, the design of the CMS Phase-2 OT, the technological choices and first results with prototype devices are reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2019

CDP1—A Data Concentrator Prototype for the Deep Underground Neutrino Experiment

The design, power analysis and tests of a first COLDATA Prototype (CDP1) design in 65nm process for the Long Baseline Neutrino Facility (LBNF) and the Deep Underground Neutrino Experiment (DUNE) are presented here. CDP1 is a prototype ASIC, for the COLDATA chip, a data concentrator operated in liquid argon. Furthermore, CDP1 is a test vehicle to qualify most of the analog and digital blocks such as LVDS transmitters and receivers, a 1.28 Gbps serializer, a phase locked loop, I 2 C for slow control, fast command receiver and calibration logic at cryogenic temperature. Finally, the test measurements of these blocks are carried out at room temperature (300K) and at cryogenic temperature (77K). The test measurements presented in this article are in good agreement with the simulation results.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2012

Building the James Webb Space Telescope

The James Webb Space Telescope is the scientific successor to the Hubble and Spitzer Space Telescopes. It will be a large (6.6m) cold (50K) telescope launched into orbit around the second Earth-Sun Lagrange point. It is a partnership of NASA with the European and Canadian Space Agencies. JWST will make progress In almost every area of astronomy, from the first galaxies to form in the early universe to exoplanets and Solar System objects. Webb will have four instruments: The Near-Infrared Camera, the Near-Infrared multi-object Spectrograph, and the Near-Infrared Imager and Slitless Spectrograph will cover the wavelength range 0.6 to 5 microns, while the Mid-Infrared Instrument will do both imaging and spectroscopy from 5 to 28.5 microns. The observatory Is confirmed for launch in 2018; the design is complete and it is in its construction phase. Innovations that make JWST possible include large-area low-noise infrared detectors, cryogenic ASICs, a MEMS micro-shutter array providing multi-object spectroscopy, a non-redundant mask for interferometric coronagraphy and diffraction-limited segmented beryllium mirrors with active wavefront sensing and control. Recent progress includes the completion of the mirrors, the delivery of the first flight instruments and the start of the integration and test phase.

Gardner, Jonathan P.↗
NASA NTRS2012

Distributed Motor Controller (DMC) for Operation in Extreme Environments

This paper presents an extreme environment capable Distributed Motor Controller (DMC) module suitable for operation with a distributed architecture of future spacecraft systems. This motor controller is designed to be a bus-based electronics module capable of operating a single Brushless DC motor in extreme space environments: temperature (-120 C to +85 C required, -180 C to +100 C stretch goal); radiation (>;20K required, >;100KRad stretch goal); >;360 cycles of operation. Achieving this objective will result in a scalable modular configuration for motor control with enhanced reliability that will greatly lower cost during the design, fabrication and ATLO phases of future missions. Within the heart of the DMC lies a pair of cold-capable Application Specific Integrated Circuits (ASICs) and a Field Programmable Gate Array (FPGA) that enable its miniaturization and operation in extreme environments. The ASICs are fabricated in the IBM 0.5 micron Silicon Germanium (SiGe) BiCMOS process and are comprised of Analog circuitry to provide telemetry information, sensor interface, and health and status of DMC. The FPGA contains logic to provide motor control, status monitoring and spacecraft interface. The testing and characterization of these ASICs have yielded excellent functionality in cold temperatures (-135 C). The DMC module has demonstrated successful operation of a motor at temperature.

SiGe↗
DOE OSTI2021

AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Un-fortunately, designing a CGRA for a specific application domain involves enormous software/hardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). Int his paper, we propose AURORA – a software/hardware co-design framework to automatically synthesize optimal CGRA given a set of applications of interest

Tan, Cheng↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
NASA NTRS1995

ASIC For Complex Fixed-Point Arithmetic

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

Petilli, Stephen G.↗
NASA NTRS2012

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Patawaran, Ferze D.↗
NASA NTRS2003

Bandwidth Efficient Baseband Multi-Modulator

The High Rate Baseband Multi-Modulator (HRBM) ASIC is being developed to provide High-speed Bandwidth Efficient Modulations to NASA missions. Bandwidth efficiencies from 2.0 bits/symbol/Hz to 2.75 bits/symbl/Hz are selectable from three CCSDS modulations: Gaussian Minimum Shift Keying (GMSK), Filter Offset Quadrature Phase Shift Keying (Filtered- OQSK) and 8-Phase Shift Keying Trellis Coded Modulation (8-PSK TCM). An FPGA version of the HRBM is developed first to verify the individual modulation designs and characterize timing and performance issues involved with digital baseband modulation synthesis. A Finite Input Response (FIR) filter is included to provided baseband pulse shaping to reduce out-of-band spectral emissions. This is filter is programmable and can be tailored to meet system requirements. The ASIC is targeted to provide up to 600 Mbps throughput and will provide serial as well as parallel input. This paper provides an overview of the technology development and current status.

Fong, Wai↗
DOE OSTI2021

Lycoris - A large-area, high resolution beam telescope

We note that a high-resolution beam telescope is one of the most important and demanding infrastructure components at any test beam facility. Its main purpose is to provide reference particle tracks from the incoming test beam particles to the test beam users, which allows measurement of the performance of the device-under-test (DUT). LYCORIS, a six-plane compact beam telescope with an active area of ~ 10 x 10 cm 2 (extensible to 10 x 20 cm 2 ) was installed at the DESY II Test Beam Facility in 2019, to provide a precise momentum measurement in a 1 T solenoid magnet or to provide tracking over a large area. The overall design of Lycoris will be described as well as the performance of the chosen silicon sensor. The 25 μm pitch micro-strip sensor used for Lycoris was originally designed for the SiD detector concept for the International Linear Collider. It adopts a second metallization layer to route signals from strips to the bump-bonded KPiX ASIC and uses a wire-bonded flex cable for the connection to the DAQ and the power supply system. This arrangement eliminates the need for a dedicated hybrid PCB. Its performance was tested for the first time in this project. The system has been evaluated at the DESY II Test Beam Facility in several test-beam campaigns and has demonstrated an average single-point resolution of 7.07 μm.

47 OTHER INSTRUMENTATION↗
NASA NTRS2007

Advanced High-Definition Video Cameras

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Glenn, William↗